Scanner hardware will generate an interrupt when any of the following events occur:
- The last memory location (as
determined by the SCANHADR registers) has been read and the data loaded
into the CRCDATA registers
- The SCANLADR register pair points to an invalid address location
- The CRCGO and/or CRCEN bits are cleared
When the last memory location has been scanned and the data has been entered into the
CRCDATA registers, scanner hardware clears
SGO and sets the Scanner Interrupt Flag (SCANIF) bit in the PIR
registers.
If the SCANLADR registers point to an invalid address location, or the CRCGO and/or CRCEN
bits are cleared, scanner hardware clears SGO, sets SCANIF, and sets the Scan Abort
Signal (
DABORT) bit.
The SCANIF bit can only be cleared by software. If the Scanner Interrupt Enable (SCANIE)
bit is set and hardware sets SCANIF, an interrupt event will occur.