PWMxCLK

Name:
PWMxCLK
Offset:
0x048D,0x050D
Reset:
Access:
Bit76543210
CLK[3:0]
AccessR/WR/WR/WR/W
Reset0000

Bits 3:0 – CLK[3:0]: PWM Clock Source Select

PWM Clock Source Select

CLK Source Operates in Sleep
1111 Reserved N/A
1110 CLC4_OUT Yes(1)
1101 CLC3_OUT Yes(1)
1100 CLC2_OUT Yes(1)
1011 CLC1_OUT Yes(1)
1010 NCO1_OUT Yes(1)
1001 CLKR_OUT Yes(1)
1000 EXTOSC Yes
0111 SOSC Yes
0110 MFINTOSC (32 kHz) Yes
0101 MFINTOSC (500 kHz) Yes
0100 LFINTOSC Yes
0011 HFINTOSC Yes
0010 FOSC No
0001 PWMIN1PPS Yes(1)
0000 PWMIN0PPS Yes(1)
Note: Operation during Sleep is possible if the clock supplying the source peripheral operates in Sleep.