When the external voltage source is sinusoidal, the effects of the
Z_{CPINV} offset can be eliminated by isolating the external voltage source from
the ZCD pin with a capacitor, in addition to the voltage reducing resistor. The capacitor
will cause a phase shift resulting in the ZCD output switch in advance of the actual
zero-crossing event. The phase shift will be the same for both rising and falling
zero-crossings, which can be compensated for by either delaying the CPU response to the ZCD
switch by a timer or other means, or selecting a capacitor value large enough that the
phase shift is negligible.

To determine the series resistor and capacitor values for this configuration, start by
computing the impedance, Z, to obtain a peak current less than the maximum input current
(ZC02). Refer to the **"Electrical Specifications"** chapter for more details. Next,
arbitrarily select a suitably large nonpolar capacitor and compute its reactance, Xc, at
the external voltage source frequency. Finally, compute the series resistor, capacitor peak
voltage, and phase shift using the formulas shown below.

When this technique is used and the input signal is not present, the
ZCD will tend to oscillate. To avoid this oscillation, connect the ZCD pin to
V_{DD} or GND with a high-impedance resistor.

Note: In this example, the impedance value
is calculated for a peak current of 300 μA.

Figure 1. R-C Equations

V_{PEAK} = external voltage source peak voltage

f = external voltage source frequency

C = series capacitor

R = series resistor

V_{C} = peak capacitor voltage

Φ = capacitor induced zero-crossing phase advance in radians

T_{Φ} = time ZC event occurs before actual zero-crossing

Figure 2. R-C Calculation Example