ADCLK

ADC Clock divider Register
Note: ADC Clock divider is only available if FOSC is selected as the ADC clock source (CS = 0).
Name:
ADCLK
Offset:
0x1D2D
Reset:
Access:
Bit76543210
CS[5:0]
AccessR/WR/WR/WR/WR/WR/W
Reset000000

Bits 5:0 – CS[5:0]: ADC Clock divider Select

ADC Clock divider Select

ValueDescription
n ADC Clock frequency = FOSC/(2*(n+1))