Register Summary - Reference CLK
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x00
...
0x0295
Reserved
0x0296
CLKRCON
7:0
EN
DC[1:0]
DIV[2:0]
0x0297
CLKRCLK
7:0
CLK[3:0]
Parent topic:
CLKREF - Reference Clock Output Module