Contents
Introduction
Features
3. Description
4. Configuration Summary
5. Ordering Information
5.1. SAM L21J
5.2. SAM L21G
5.3. SAM L21E
5.4. Device Identification
6. Block Diagram
7. Pinout
7.1. SAM L21J
7.2. SAM L21J WLCSP64
7.3. SAM L21G
7.4. SAM L21E
8. Signal Descriptions List
9. I/O Multiplexing and Considerations
9.1. Multiplexed Signals
9.2. Other Functions
9.2.1. Oscillator Pinout
9.2.2. Serial Wire Debug Interface Pinout
9.2.3. Supply Controller Pinout
9.2.4. SERCOM I2C Pins
9.2.5. GPIO Clusters
9.2.6. TCC Configurations
10. Analog Connections of Peripherals
10.1. Block Diagram
10.2. Analog Connections
10.3. Reference Voltages
10.4. Analog ONDEMAND Function
11. Power Supply and Start-Up Considerations
11.1. Power Domain Overview
11.2. Power Supply Considerations
11.2.1. Power Supplies
11.2.2. Voltage Regulator
11.2.3. Typical Powering Schematic
11.2.4. Power-Up Sequence
11.2.4.1. Supply Order
11.2.4.2. Minimum Rise Rate
11.2.4.3. Maximum Rise Rate
11.3. Power-Up
11.3.1. Starting of Internal Regulator
11.3.2. Starting of Clocks
11.3.3. I/O Pins
11.3.4. Fetching of Initial Instructions
11.4. Power-On Reset and Brown-Out Detector
11.4.1. Power-On Reset on VDDIN
11.4.2. Power-On Reset on VSWOUT
11.4.3. Power-On Reset on VDDIO
11.4.4. Brown-Out Detector on VSWOUT/VBAT
11.4.5. Brown-Out Detector on VDDCORE
11.5. Performance Level Overview
12. Product Mapping
13. Memories
13.1. Embedded Memories
13.2. Physical Memory Map
13.3. NVM User Row Mapping
13.4. NVM Software Calibration Area Mapping
13.5. NVM Temperature Log Row
13.6. Serial Number
14. Processor and Architecture
14.1. Cortex M0+ Processor
14.1.1. Cortex M0+ Configuration
14.1.1.1. Cortex M0+ Peripherals
14.1.1.2. Cortex M0+ Address Map
14.1.1.3. I/O Interface
14.2. Nested Vector Interrupt Controller
14.2.1. Overview
14.2.2. Interrupt Line Mapping
14.3. Micro Trace Buffer
14.3.1. Features
14.3.2. Overview
14.4. High-Speed Bus System
14.4.1. Overview
14.4.2. Features
14.4.3. Configuration
14.4.4. SRAM Quality of Service
15. PAC - Peripheral Access Controller
15.1. Overview
15.2. Features
15.3. Block Diagram
15.4. Product Dependencies
15.4.1. I/O Lines
15.4.2. Power Management
15.4.3. Clocks
15.4.4. DMA
15.4.5. Interrupts
15.4.6. Events
15.4.7. Debug Operation
15.4.8. Register Access Protection
15.5. Functional Description
15.5.1. Principle of Operation
15.5.2. Basic Operation
15.5.2.1. Initialization, Enabling and Resetting
15.5.2.2. Operations
15.5.2.3. Peripheral Access Errors
15.5.2.4. Write Access Protection Management
15.5.2.5. Write Access Protection Management Errors
15.5.2.6. AHB Slave Bus Errors
15.5.2.7. Generating Events
15.5.3. DMA Operation
15.5.4. Interrupts
15.5.5. Events
15.5.6. Sleep Mode Operation
15.5.7. Synchronization
15.6. Register Summary
15.7. Register Description
15.7.1. Write Control
15.7.2. Event Control
15.7.3. Interrupt Enable Clear
15.7.4. Interrupt Enable Set
15.7.5. AHB Slave Bus Interrupt Flag Status and Clear
15.7.6. Peripheral Interrupt Flag Status and Clear A
15.7.7. Peripheral Interrupt Flag Status and Clear B
15.7.8. Peripheral Interrupt Flag Status and Clear C
15.7.9. Peripheral Interrupt Flag Status and Clear D
15.7.10. Peripheral Interrupt Flag Status and Clear E
15.7.11. Peripheral Write Protection Status A
15.7.12. Peripheral Write Protection Status B
15.7.13. Peripheral Write Protection Status C
15.7.14. Peripheral Write Protection Status D
15.7.15. Peripheral Write Protection Status E
16. Peripherals Configuration Summary
17. DSU - Device Service Unit
17.1. Overview
17.2. Features
17.3. Block Diagram
17.4. Signal Description
17.5. Product Dependencies
17.5.1. IO Lines
17.5.2. Power Management
17.5.3. Clocks
17.5.4. Interrupts
17.5.5. Events
17.5.6. Register Access Protection
17.5.7. Analog Connections
17.6. Debug Operation
17.6.1. Principle of Operation
17.6.2. CPU Reset Extension
17.6.3. Debugger Probe Detection
17.6.3.1. Cold Plugging
17.6.3.2. Hot Plugging
17.7. Chip Erase
17.8. Programming
17.9. Intellectual Property Protection
17.10. Device Identification
17.10.1. CoreSight Identification
17.10.2. Chip Identification Method
17.11. Functional Description
17.11.1. Principle of Operation
17.11.2. Basic Operation
17.11.2.1. Initialization
17.11.2.2. Operation From a Debug Adapter
17.11.2.3. Operation From the CPU
17.11.3. 32-bit Cyclic Redundancy Check CRC32
17.11.3.1. Starting CRC32 Calculation
17.11.3.2. Interpreting the Results
17.11.4. Debug Communication Channels
17.11.5. Testing of On-Board Memories MBIST
17.11.6. System Services Availability when Accessed Externally
17.12. Register Summary
17.13. Register Description
17.13.1. Control
17.13.2. Status A
17.13.3. Status B
17.13.4. Address
17.13.5. Length
17.13.6. Data
17.13.7. Debug Communication Channel 0
17.13.8. Debug Communication Channel 1
17.13.9. Device Identification
17.13.10. CoreSight ROM Table Entry 0
17.13.11. CoreSight ROM Table Entry 1
17.13.12. CoreSight ROM Table End
17.13.13. CoreSight ROM Table Memory Type
17.13.14. Peripheral Identification 4
17.13.15. Peripheral Identification 0
17.13.16. Peripheral Identification 1
17.13.17. Peripheral Identification 2
17.13.18. Peripheral Identification 3
17.13.19. Component Identification 0
17.13.20. Component Identification 1
17.13.21. Component Identification 2
17.13.22. Component Identification 3
18. Clock System
18.1. Clock Distribution
18.2. Synchronous and Asynchronous Clocks
18.3. Register Synchronization
18.3.1. Overview
18.3.2. General Write Synchronization
18.3.3. General Read Synchronization
18.3.4. Completion of Synchronization
18.3.5. Enable Write Synchronization
18.3.6. Software Reset Write-Synchronization
18.3.7. Synchronization Delay
18.4. Enabling a Peripheral
18.5. On Demand Clock Requests
18.6. Power Consumption vs. Speed
18.7. Clocks after Reset
19. GCLK - Generic Clock Controller
19.1. Overview
19.2. Features
19.3. Block Diagram
19.4. Signal Description
19.5. Product Dependencies
19.5.1. I/O Lines
19.5.2. Power Management
19.5.3. Clocks
19.5.4. DMA
19.5.5. Interrupts
19.5.6. Events
19.5.7. Debug Operation
19.5.8. Register Access Protection
19.5.9. Analog Connections
19.6. Functional Description
19.6.1. Principle of Operation
19.6.1.1. Basic Operation
19.6.1.1.1. Initialization
19.6.1.1.2. Enabling, Disabling, and Resetting
19.6.1.1.3. Generic Clock Generator
19.6.1.1.4. Enabling a Generator
19.6.1.1.5. Disabling a Generator
19.6.1.1.6. Selecting a Clock Source for the Generator
19.6.1.1.7. Changing the Clock Frequency
19.6.1.1.8. Duty Cycle
19.6.1.1.9. External Clock
19.6.2. Peripheral Clock
19.6.2.1. Enabling a Peripheral Clock
19.6.2.2. Disabling a Peripheral Clock
19.6.2.3. Selecting the Clock Source for a Peripheral
19.6.2.4. Configuration Lock
19.6.3. Synchronization
19.7. Sleep Mode Operation
19.7.1. SleepWalking
19.7.2. Minimize Power Consumption in Standby
19.7.3. Entering Standby Mode
19.8. Additional Features
19.8.1. Peripheral Clock Enable after Reset
19.9. Register Summary
19.10. Register Description
19.10.1. Control A
19.10.2. Synchronization Busy
19.10.3. Generator Control
19.10.4. Peripheral Channel Control
20. MCLK – Main Clock
20.1. Overview
20.2. Features
20.3. Block Diagram
20.4. Signal Description
20.5. Product Dependencies
20.5.1. I/O Lines
20.5.2. Power Management
20.5.3. Clocks
20.5.3.1. Main Clock
20.5.3.2. CPU Clock
20.5.3.3. APBx and AHBx Clock
20.5.3.4. Clock Domains
20.5.4. DMA
20.5.5. Interrupts
20.5.6. Events
20.5.7. Debug Operation
20.5.8. Register Access Protection
20.5.9. Analog Connections
20.6. Functional Description
20.6.1. Principle of Operation
20.6.2. Basic Operation
20.6.2.1. Initialization
20.6.2.2. Enabling, Disabling, and Resetting
20.6.2.3. Selecting the Main Clock Source
20.6.2.4. Selecting the Synchronous Clock Division Ratio
20.6.2.5. Clock Ready Flag
20.6.2.6. Peripheral Clock Masking
20.6.3. DMA Operation
20.6.4. Interrupts
20.6.5. Events
20.6.6. Sleep Mode Operation
20.7. Register Summary - MCLK
20.8. Register Description
20.8.1. Control A
20.8.2. Interrupt Enable Clear
20.8.3. Interrupt Enable Set
20.8.4. Interrupt Flag Status and Clear
20.8.5. CPU Clock Division
20.8.6. Low Power Clock Division
20.8.7. Backup Clock Division
20.8.8. AHB Mask
20.8.9. APBA Mask
20.8.10. APBB Mask
20.8.11. APBC Mask
20.8.12. APBD Mask
20.8.13. APBE Mask
21. RSTC – Reset Controller
21.1. Overview
21.2. Features
21.3. Block Diagram
21.4. Signal Description
21.5. Product Dependencies
21.5.1. I/O Lines
21.5.2. Power Management
21.5.3. Clocks
21.5.4. DMA
21.5.5. Interrupts
21.5.6. Events
21.5.7. Debug Operation
21.5.8. Register Access Protection
21.5.9. Analog Connections
21.6. Functional Description
21.6.1. Principle of Operation
21.6.2. Basic Operation
21.6.2.1. Initialization
21.6.2.2. Enabling, Disabling, and Resetting
21.6.2.3. External Wake-Up Detector
21.6.2.4. Reset Causes and Effects
21.6.3. Additional Features
21.6.4. DMA Operation
21.6.5. Interrupts
21.6.6. Events
21.6.7. Sleep Mode Operation
21.7. Register Summary
21.8. Register Description
21.8.1. Reset Cause
21.8.2. Backup Exit Source
21.8.3. Wakeup Debounce Configuration
21.8.4. Wakeup Polarity
21.8.5. Wakeup Enable
21.8.6. Wakeup Cause
22. PM – Power Manager
22.1. Overview
22.2. Features
22.3. Block Diagram
22.4. Signal Description
22.5. Product Dependencies
22.5.1. I/O Lines
22.5.2. Clocks
22.5.3. DMA
22.5.4. Interrupts
22.5.5. Events
22.5.6. Debug Operation
22.5.7. Register Access Protection
22.5.8. Analog Connections
22.6. Functional Description
22.6.1. Terminology
22.6.1.1. Performance Levels
22.6.1.2. Power Domains
22.6.1.3. Sleep Modes
22.6.1.4. Power Domain States and Gating
22.6.2. Principle of Operation
22.6.3. Basic Operation
22.6.3.1. Initialization
22.6.3.2. Enabling, Disabling and Resetting
22.6.3.3. Sleep Mode Controller
22.6.3.4. I/O Lines Retention in BACKUP Mode
22.6.3.5. Performance Level
22.6.3.6. Power Domain Controller
22.6.3.7. Regulators, RAMs, and NVM State in Sleep Mode
22.6.4. Advanced Features
22.6.4.1. Power Domain Configuration
22.6.4.2. Linked Power Domains
22.6.4.3. RAM Automatic Low Power Mode
22.6.4.4. Regulator Automatic Low Power Mode
22.6.4.5. SleepWalking and Performance Level
22.6.4.6. Wake-Up Time
22.6.5. SleepWalking with Static Power Domain Gating in Details
22.6.6. Sleepwalking with Dynamic Power Domain Gating in Details
22.6.6.1. Dynamic SleepWalking on Bus Transaction
22.6.6.2. Dynamic SleepWalking based on Event
22.6.6.3. Dynamic SleepWalking Based on Peripheral DMA Trigger
22.6.7. DMA Operation
22.6.8. Interrupts
22.6.9. Events
22.6.10. Sleep Mode Operation
22.7. Register Summary
22.8. Register Description
22.8.1. Control A
22.8.2. Sleep Configuration
22.8.3. Performance Level Configuration
22.8.4. Interrupt Enable Clear
22.8.5. Interrupt Enable Set
22.8.6. Interrupt Flag Status and Clear
22.8.7. Standby Configuration
22.8.8. Power Switch Acknowledge Delay
23. OSCCTRL – Oscillators Controller
23.1. Overview
23.2. Features
23.3. Block Diagram
23.4. Signal Description
23.5. Product Dependencies
23.5.1. I/O Lines
23.5.2. Power Management
23.5.3. Clocks
23.5.4. DMA
23.5.5. Interrupts
23.5.6. Debug Operation
23.5.7. Register Access Protection
23.5.8. Analog Connections
23.6. Functional Description
23.6.1. Principle of Operation
23.6.2. External Multipurpose Crystal Oscillator (XOSC) Operation
23.6.3. 16MHz Internal Oscillator (OSC16M) Operation
23.6.4. Digital Frequency Locked Loop (DFLL48M) Operation
23.6.4.1. Basic Operation
23.6.4.2. Additional Features
23.6.5. Digital Phase Locked Loop (DPLL) Operation
23.6.5.1. Basic Operation
23.6.6. DMA Operation
23.6.7. Interrupts
23.6.8. Events
23.6.9. Synchronization
23.7. Register Summary
23.8. Register Description
23.8.1. Interrupt Enable Set
23.8.2. Interrupt Enable Clear
23.8.3. Interrupt Flag Status and Clear
23.8.4. Status
23.8.5. External Multipurpose Crystal Oscillator (XOSC) Control
23.8.6. 16MHz Internal Oscillator (OSC16M) Control
23.8.7. DFLL48M Control
23.8.8. DFLL48M Value
23.8.9. DFLL48M Multiplier
23.8.10. DFLL48M Synchronization
23.8.11. DPLL Control A
23.8.12. DPLL Ratio Control
23.8.13. DPLL Control B
23.8.14. DPLL Prescaler
23.8.15. DPLL Synchronization Busy
23.8.16. DPLL Status
24. OSC32KCTRL – 32KHz Oscillators Controller
24.1. Overview
24.2. Features
24.3. Block Diagram
24.4. Signal Description
24.5. Product Dependencies
24.5.1. I/O Lines
24.5.2. Power Management
24.5.3. Clocks
24.5.4. Interrupts
24.5.5. Debug Operation
24.5.6. Register Access Protection
24.5.7. Analog Connections
24.5.8. Calibration
24.6. Functional Description
24.6.1. Principle of Operation
24.6.2. 32KHz External Crystal Oscillator (XOSC32K) Operation
24.6.3. 32KHz Internal Oscillator (OSC32K) Operation
24.6.4. 32KHz Ultra Low Power Internal Oscillator (OSCULP32K) Operation
24.6.5. Watchdog Timer Clock Selection
24.6.6. Real-Time Counter Clock Selection
24.6.7. Interrupts
24.7. Register Summary
24.8. Register Description
24.8.1. Interrupt Enable Clear
24.8.2. Interrupt Enable Set
24.8.3. Interrupt Flag Status and Clear
24.8.4. Status
24.8.5. RTC Clock Selection Control
24.8.6. 32KHz External Crystal Oscillator (XOSC32K) Control
24.8.7. 32KHz Internal Oscillator (OSC32K) Control
24.8.8. 32KHz Ultra Low Power Internal Oscillator (OSCULP32K) Control
25. SUPC – Supply Controller
25.1. Overview
25.2. Features
25.3. Block Diagram
25.4. Signal Description
25.5. Product Dependencies
25.5.1. I/O Lines
25.5.2. Power Management
25.5.3. Clocks
25.5.4. DMA
25.5.5. Interrupts
25.5.6. Events
25.5.7. Debug Operation
25.5.8. Register Access Protection
25.5.9. Analog Connections
25.6. Functional Description
25.6.1. Voltage Regulator System Operation
25.6.1.1. Enabling, Disabling, and Resetting
25.6.1.2. Initialization
25.6.1.3. Selecting a Voltage Regulator
25.6.1.4. Voltage Scaling Control
25.6.1.5. Sleep Mode Operation
25.6.2. Voltage Reference System Operation
25.6.2.1. Initialization
25.6.2.2. Enabling, Disabling, and Resetting
25.6.2.3. Selecting a Voltage Reference
25.6.2.4. Sleep Mode Operation
25.6.3. Battery Backup Power Switch
25.6.3.1. Initialization
25.6.3.2. Forced Battery Backup Power Switch
25.6.3.3. Automatic Battery Backup Power Switch
25.6.3.4. Sleep Mode Operation
25.6.3.4.1. Entering Battery Backup Mode
25.6.3.4.2. Leaving Battery Backup Mode
25.6.4. Output Pins
25.6.5. Brown-Out Detectors
25.6.5.1. Initialization
25.6.5.2. Enabling, Disabling, and Resetting
25.6.5.3. Brown-Out Detector (BOD33)
25.6.5.4. Brown-Out Detector (BOD12)
25.6.5.5. Continuous Mode
25.6.5.6. Sampling Mode
25.6.5.7. Hysteresis
25.6.5.8. Sleep Mode Operation
25.6.6. Interrupts
25.6.7. Synchronization
25.7. Register Summary
25.8. Register Description
25.8.1. Interrupt Enable Clear
25.8.2. Interrupt Enable Set
25.8.3. Interrupt Flag Status and Clear
25.8.4. Status
25.8.5. Brown-Out Detector (BOD33) Control
25.8.6. Voltage Regulator System (VREG) Control
25.8.7. Voltage References System (VREF) Control
25.8.8. Battery Backup Power Switch (BBPS) Control
25.8.9. Backup Output (BKOUT) Control
25.8.10. Backup Input (BKIN) Value
26. WDT – Watchdog Timer
26.1. Overview
26.2. Features
26.3. Block Diagram
26.4. Signal Description
26.5. Product Dependencies
26.5.1. I/O Lines
26.5.2. Power Management
26.5.3. Clocks
26.5.4. DMA
26.5.5. Interrupts
26.5.6. Events
26.5.7. Debug Operation
26.5.8. Register Access Protection
26.5.9. Analog Connections
26.6. Functional Description
26.6.1. Principle of Operation
26.6.2. Basic Operation
26.6.2.1. Initialization
26.6.2.2. Configurable Reset Values
26.6.2.3. Enabling, Disabling, and Resetting
26.6.2.4. Normal Mode
26.6.2.5. Window Mode
26.6.3. DMA Operation
26.6.4. Interrupts
26.6.5. Events
26.6.6. Sleep Mode Operation
26.6.7. Synchronization
26.6.8. Additional Features
26.6.8.1. Always-On Mode
26.6.8.2. Early Warning
26.7. Register Summary
26.8. Register Description
26.8.1. Control A
26.8.2. Configuration
26.8.3. Early Warning Control
26.8.4. Interrupt Enable Clear
26.8.5. Interrupt Enable Set
26.8.6. Interrupt Flag Status and Clear
26.8.7. Synchronization Busy
26.8.8. Clear
27. RTC – Real-Time Counter
27.1. Overview
27.2. Features
27.3. Block Diagram
27.4. Signal Description
27.5. Product Dependencies
27.5.1. I/O Lines
27.5.2. Power Management
27.5.3. Clocks
27.5.4. DMA
27.5.5. Interrupts
27.5.6. Events
27.5.7. Debug Operation
27.5.8. Register Access Protection
27.5.9. Analog Connections
27.6. Functional Description
27.6.1. Principle of Operation
27.6.2. Basic Operation
27.6.2.1. Initialization
27.6.2.2. Enabling, Disabling, and Resetting
27.6.2.3. 32-Bit Counter (Mode 0)
27.6.2.4. 16-Bit Counter (Mode 1)
27.6.2.5. Clock/Calendar (Mode 2)
27.6.3. DMA Operation
27.6.4. Interrupts
27.6.5. Events
27.6.6. Sleep Mode Operation
27.6.7. Synchronization
27.6.8. Additional Features
27.6.8.1. Periodic Intervals
27.6.8.2. Frequency Correction
27.6.8.3. General Purpose Registers
27.7. Register Summary - COUNT32
27.8. Register Description - COUNT32
27.8.1. Control A in COUNT32 mode (CTRLA.MODE=0)
27.8.2. Event Control in COUNT32 mode (CTRLA.MODE=0)
27.8.3. Interrupt Enable Clear in COUNT32 mode (CTRLA.MODE=0)
27.8.4. Interrupt Enable Set in COUNT32 mode (CTRLA.MODE=0)
27.8.5. Interrupt Flag Status and Clear in COUNT32 mode (CTRLA.MODE=0)
27.8.6. Debug Control
27.8.7. Synchronization Busy in COUNT32 mode (CTRLA.MODE=0)
27.8.8. Frequency Correlation
27.8.9. Counter Value in COUNT32 mode (CTRLA.MODE=0)
27.8.10. Compare 0 Value in COUNT32 mode (CTRLA.MODE=0)
27.8.11. General Purpose n
27.9. Register Summary - COUNT16
27.10. Register Description - COUNT16
27.10.1. Control A in COUNT16 mode (CTRLA.MODE=1)
27.10.2. Event Control in COUNT16 mode (CTRLA.MODE=1)
27.10.3. Interrupt Enable Clear in COUNT16 mode (CTRLA.MODE=1)
27.10.4. Interrupt Enable Set in COUNT16 mode (CTRLA.MODE=1)
27.10.5. Interrupt Flag Status and Clear in COUNT16 mode (CTRLA.MODE=1)
27.10.6. Debug Control
27.10.7. Synchronization Busy in COUNT16 mode (CTRLA.MODE=1)
27.10.8. Frequency Correlation
27.10.9. Counter Value in COUNT16 mode (CTRLA.MODE=1)
27.10.10. Counter Period in COUNT16 mode (CTRLA.MODE=1)
27.10.11. Compare n Value in COUNT16 mode (CTRLA.MODE=1)
27.10.12. General Purpose n
27.11. Register Summary - CLOCK
27.12. Register Description - CLOCK
27.12.1. Control A in Clock/Calendar mode (CTRLA.MODE=2)
27.12.2. Event Control in Clock/Calendar mode (CTRLA.MODE=2)
27.12.3. Interrupt Enable Clear in Clock/Calendar mode (CTRLA.MODE=2)
27.12.4. Interrupt Enable Set in Clock/Calendar mode (CTRLA.MODE=2)
27.12.5. Interrupt Flag Status and Clear in Clock/Calendar mode (CTRLA.MODE=2)
27.12.6. Debug Control
27.12.7. Synchronization Busy in Clock/Calendar mode (CTRLA.MODE=2)
27.12.8. Frequency Correlation
27.12.9. Clock Value in Clock/Calendar mode (CTRLA.MODE=2)
27.12.10. Alarm Value in Clock/Calendar mode (CTRLA.MODE=2)
27.12.11. Alarm Mask in Clock/Calendar mode (CTRLA.MODE=2)
27.12.12. General Purpose n
28. DMAC – Direct Memory Access Controller
28.1. Overview
28.2. Features
28.3. Block Diagram
28.4. Signal Description
28.5. Product Dependencies
28.5.1. I/O Lines
28.5.2. Power Management
28.5.3. Clocks
28.5.4. DMA
28.5.5. Interrupts
28.5.6. Events
28.5.7. Debug Operation
28.5.8. Register Access Protection
28.5.9. Analog Connections
28.6. Functional Description
28.6.1. Principle of Operation
28.6.1.1. DMA
28.6.1.2. CRC
28.6.2. Basic Operation
28.6.2.1. Initialization
28.6.2.2. Enabling, Disabling, and Resetting
28.6.2.3. Transfer Descriptors
28.6.2.4. Arbitration
28.6.2.5. Data Transmission
28.6.2.6. Transfer Triggers and Actions
28.6.2.7. Addressing
28.6.2.8. Error Handling
28.6.3. Additional Features
28.6.3.1. Linked Descriptors
28.6.3.1.1. Adding Descriptor to the End of a List
28.6.3.1.2. Modifying a Descriptor in a List
28.6.3.1.3. Adding a Descriptor Between Existing Descriptors
28.6.3.2. Channel Suspend
28.6.3.3. Channel Resume and Next Suspend Skip
28.6.3.4. Event Input Actions
28.6.3.5. Event Output Selection
28.6.3.6. Aborting Transfers
28.6.3.7. CRC Operation
28.6.4. DMA Operation
28.6.5. Interrupts
28.6.6. Events
28.6.7. Sleep Mode Operation
28.6.8. Synchronization
28.7. Register Summary
28.8. Register Description
28.8.1. Control
28.8.2. CRC Control
28.8.3. CRC Data Input
28.8.4. CRC Checksum
28.8.5. CRC Status
28.8.6. Debug Control
28.8.7. Quality of Service Control
28.8.8. Software Trigger Control
28.8.9. Priority Control 0
28.8.10. Interrupt Pending
28.8.11. Interrupt Status
28.8.12. Busy Channels
28.8.13. Pending Channels
28.8.14. Active Channel and Levels
28.8.15. Descriptor Memory Section Base Address
28.8.16. Write-Back Memory Section Base Address
28.8.17. Channel ID
28.8.18. Channel Control A
28.8.19. Channel Control B
28.8.20. Channel Interrupt Enable Clear
28.8.21. Channel Interrupt Enable Set
28.8.22. Channel Interrupt Flag Status and Clear
28.8.23. Channel Status
28.9. Register Summary - LP SRAM
28.10. Register Description - LP SRAM
28.10.1. Block Transfer Control
28.10.2. Block Transfer Count
28.10.3. Block Transfer Source Address
28.10.4. Block Transfer Destination Address
28.10.5. Next Descriptor Address
29. EIC – External Interrupt Controller
29.1. Overview
29.2. Features
29.3. Block Diagram
29.4. Signal Description
29.5. Product Dependencies
29.5.1. I/O Lines
29.5.2. Power Management
29.5.3. Clocks
29.5.4. DMA
29.5.5. Interrupts
29.5.6. Events
29.5.7. Debug Operation
29.5.8. Register Access Protection
29.5.9. Analog Connections
29.6. Functional Description
29.6.1. Principle of Operation
29.6.2. Basic Operation
29.6.2.1. Initialization
29.6.2.2. Enabling, Disabling, and Resetting
29.6.3. External Pin Processing
29.6.4. Additional Features
29.6.4.1. Non-Maskable Interrupt (NMI)
29.6.4.2. Asynchronous Edge Detection Mode (No Debouncing)
29.6.5. DMA Operation
29.6.6. Interrupts
29.6.7. Events
29.6.8. Sleep Mode Operation
29.6.9. Synchronization
29.7. Register Summary
29.8. Register Description
29.8.1. Control A
29.8.2. Non-Maskable Interrupt Control
29.8.3. Non-Maskable Interrupt Flag Status and Clear
29.8.4. Synchronization Busy
29.8.5. Event Control
29.8.6. Interrupt Enable Clear
29.8.7. Interrupt Enable Set
29.8.8. Interrupt Flag Status and Clear
29.8.9. External Interrupt Asynchronous Mode
29.8.10. External Interrupt Sense Configuration n
30. NVMCTRL – Non-Volatile Memory Controller
30.1. Overview
30.2. Features
30.3. Block Diagram
30.4. Signal Description
30.5. Product Dependencies
30.5.1. Power Management
30.5.2. Clocks
30.5.3. Interrupts
30.5.4. Debug Operation
30.5.5. Register Access Protection
30.5.6. Analog Connections
30.6. Functional Description
30.6.1. Principle of Operation
30.6.1.1. Initialization
30.6.2. Memory Organization
30.6.3. Region Lock Bits
30.6.4. Command and Data Interface
30.6.4.1. NVM Read
30.6.4.2. RWWEE Read
30.6.4.3. NVM Write
30.6.4.3.1. Procedure for Manual Page Writes (CTRLB.MANW=1)
30.6.4.3.2. Procedure for Automatic Page Writes (CTRLB.MANW=0)
30.6.4.4. Page Buffer Clear
30.6.4.5. Erase Row
30.6.4.6. Lock and Unlock Region
30.6.4.7. Set and Clear Power Reduction Mode
30.6.5. NVM User Configuration
30.6.6. Security Bit
30.6.7. Cache
30.7. Register Summary
30.8. Register Description
30.8.1. Control A
30.8.2. Control B
30.8.3. NVM Parameter
30.8.4. Interrupt Enable Clear
30.8.5. Interrupt Enable Set
30.8.6. Interrupt Flag Status and Clear
30.8.7. Status
30.8.8. Address
30.8.9. Lock Section
31. PORT - I/O Pin Controller
31.1. Overview
31.2. Features
31.3. Block Diagram
31.4. Signal Description
31.5. Product Dependencies
31.5.1. I/O Lines
31.5.2. Power Management
31.5.3. Clocks
31.5.4. DMA
31.5.5. Interrupts
31.5.6. Events
31.5.7. Debug Operation
31.5.8. Register Access Protection
31.5.9. Analog Connections
31.5.10. CPU Local Bus
31.6. Functional Description
31.6.1. Principle of Operation
31.6.2. Basic Operation
31.6.2.1. Initialization
31.6.2.2. Operation
31.6.3. I/O Pin Configuration
31.6.3.1. Pin Configurations Summary
31.6.3.2. Input Configuration
31.6.3.3. Totem-Pole Output
31.6.3.4. Digital Functionality Disabled
31.6.4. Events
31.6.5. PORT Access Priority
31.7. Register Summary
31.8. Register Description
31.8.1. Data Direction
31.8.2. Data Direction Clear
31.8.3. Data Direction Set
31.8.4. Data Direction Toggle
31.8.5. Data Output Value
31.8.6. Data Output Value Clear
31.8.7. Data Output Value Set
31.8.8. Data Output Value Toggle
31.8.9. Data Input Value
31.8.10. Control
31.8.11. Write Configuration
31.8.12. Event Input Control
31.8.13. Peripheral Multiplexing n
31.8.14. Pin Configuration
32. EVSYS – Event System
32.1. Overview
32.2. Features
32.3. Block Diagram
32.4. Signal Description
32.5. Product Dependencies
32.5.1. I/O Lines
32.5.2. Power Management
32.5.3. Clocks
32.5.4. DMA
32.5.5. Interrupts
32.5.6. Events
32.5.7. Debug Operation
32.5.8. Register Access Protection
32.5.9. Analog Connections
32.6. Functional Description
32.6.1. Principle of Operation
32.6.2. Basic Operation
32.6.2.1. Initialization
32.6.2.2. Enabling, Disabling, and Resetting
32.6.2.3. User Multiplexer Setup
32.6.2.4. Event System Channel
32.6.2.5. Event Generators
32.6.2.6. Channel Path
32.6.2.7. Edge Detection
32.6.2.8. Event Latency
32.6.2.9. The Overrun Channel n Interrupt
32.6.2.10. The Event Detected Channel n Interrupt
32.6.2.11. Channel Status
32.6.2.12. Software Event
32.6.3. Interrupts
32.6.4. Sleep Mode Operation
32.7. Register Summary
32.8. Register Description
32.8.1. Control A
32.8.2. Channel Status
32.8.3. Interrupt Enable Clear
32.8.4. Interrupt Enable Set
32.8.5. Interrupt Flag Status and Clear
32.8.6. Software Event
32.8.7. Channel
32.8.8. Event User m
33. SERCOM – Serial Communication Interface
33.1. Overview
33.2. Features
33.3. Block Diagram
33.4. Signal Description
33.5. Product Dependencies
33.5.1. I/O Lines
33.5.2. Power Management
33.5.3. Clocks
33.5.4. DMA
33.5.5. Interrupts
33.5.6. Events
33.5.7. Debug Operation
33.5.8. Register Access Protection
33.5.9. Analog Connections
33.6. Functional Description
33.6.1. Principle of Operation
33.6.2. Basic Operation
33.6.2.1. Initialization
33.6.2.2. Enabling, Disabling, and Resetting
33.6.2.3. Clock Generation – Baud-Rate Generator
33.6.3. Additional Features
33.6.3.1. Address Match and Mask
33.6.4. DMA Operation
33.6.5. Interrupts
33.6.6. Events
33.6.7. Sleep Mode Operation
33.6.8. Synchronization
34. SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter
34.1. Overview
34.2. USART Features
34.3. Block Diagram
34.4. Signal Description
34.5. Product Dependencies
34.5.1. I/O Lines
34.5.2. Power Management
34.5.3. Clocks
34.5.4. DMA
34.5.5. Interrupts
34.5.6. Events
34.5.7. Debug Operation
34.5.8. Register Access Protection
34.5.9. Analog Connections
34.6. Functional Description
34.6.1. Principle of Operation
34.6.2. Basic Operation
34.6.2.1. Initialization
34.6.2.2. Enabling, Disabling, and Resetting
34.6.2.3. Clock Generation and Selection
34.6.2.4. Data Register
34.6.2.5. Data Transmission
34.6.2.6. Data Reception
34.6.3. Additional Features
34.6.3.1. Parity
34.6.3.2. Hardware Handshaking
34.6.3.3. IrDA Modulation and Demodulation
34.6.3.4. Break Character Detection and Auto-Baud
34.6.3.5. Collision Detection
34.6.3.6. Loop-Back Mode
34.6.3.7. Start-of-Frame Detection
34.6.3.8. Sample Adjustment
34.6.4. DMA, Interrupts and Events
34.6.4.1. DMA Operation
34.6.4.2. Interrupts
34.6.4.3. Events
34.6.5. Sleep Mode Operation
34.6.6. Synchronization
34.7. Register Summary
34.8. Register Description
34.8.1. Control A
34.8.2. Control B
34.8.3. Baud
34.8.4. Receive Pulse Length Register
34.8.5. Interrupt Enable Clear
34.8.6. Interrupt Enable Set
34.8.7. Interrupt Flag Status and Clear
34.8.8. Status
34.8.9. Synchronization Busy
34.8.10. Data
34.8.11. Debug Control
35. SERCOM SPI – SERCOM Serial Peripheral Interface
35.1. Overview
35.2. Features
35.3. Block Diagram
35.4. Signal Description
35.5. Product Dependencies
35.5.1. I/O Lines
35.5.2. Power Management
35.5.3. Clocks
35.5.4. DMA
35.5.5. Interrupts
35.5.6. Events
35.5.7. Debug Operation
35.5.8. Register Access Protection
35.5.9. Analog Connections
35.6. Functional Description
35.6.1. Principle of Operation
35.6.2. Basic Operation
35.6.2.1. Initialization
35.6.2.2. Enabling, Disabling, and Resetting
35.6.2.3. Clock Generation
35.6.2.4. Data Register
35.6.2.5. SPI Transfer Modes
35.6.2.6. Transferring Data
35.6.2.7. Receiver Error Bit
35.6.3. Additional Features
35.6.3.1. Address Recognition
35.6.3.2. Preloading of the Slave Shift Register
35.6.3.3. Master with Several Slaves
35.6.3.4. Loop-Back Mode
35.6.3.5. Hardware Controlled SS
35.6.3.6. Slave Select Low Detection
35.6.4. DMA, Interrupts, and Events
35.6.4.1. DMA Operation
35.6.4.2. Interrupts
35.6.4.3. Events
35.6.5. Sleep Mode Operation
35.6.6. Synchronization
35.7. Register Summary
35.8. Register Description
35.8.1. Control A
35.8.2. Control B
35.8.3. Baud Rate
35.8.4. Interrupt Enable Clear
35.8.5. Interrupt Enable Set
35.8.6. Interrupt Flag Status and Clear
35.8.7. Status
35.8.8. Synchronization Busy
35.8.9. Address
35.8.10. Data
35.8.11. Debug Control
36. SERCOM I2C – SERCOM Inter-Integrated Circuit
36.1. Overview
36.2. Features
36.3. Block Diagram
36.4. Signal Description
36.5. Product Dependencies
36.5.1. I/O Lines
36.5.2. Power Management
36.5.3. Clocks
36.5.4. DMA
36.5.5. Interrupts
36.5.6. Events
36.5.7. Debug Operation
36.5.8. Register Access Protection
36.5.9. Analog Connections
36.6. Functional Description
36.6.1. Principle of Operation
36.6.2. Basic Operation
36.6.2.1. Initialization
36.6.2.2. Enabling, Disabling, and Resetting
36.6.2.3. I2C Bus State Logic
36.6.2.4. I2C Master Operation
36.6.2.5. I2C Slave Operation
36.6.3. Additional Features
36.6.3.1. SMBus
36.6.3.2. Smart Mode
36.6.3.3. 4-Wire Mode
36.6.3.4. Quick Command
36.6.4. DMA, Interrupts and Events
36.6.4.1. DMA Operation
36.6.4.2. Interrupts
36.6.4.3. Events
36.6.5. Sleep Mode Operation
36.6.6. Synchronization
36.7. Register Summary - I2C Slave
36.8. Register Description - I2C Slave
36.8.1. Control A
36.8.2. Control B
36.8.3. Interrupt Enable Clear
36.8.4. Interrupt Enable Set
36.8.5. Interrupt Flag Status and Clear
36.8.6. Status
36.8.7. Synchronization Busy
36.8.8. Address
36.8.9. Data
36.9. Register Summary - I2C Master
36.10. Register Description - I2C Master
36.10.1. Control A
36.10.2. Control B
36.10.3. Baud Rate
36.10.4. Interrupt Enable Clear
36.10.5. Interrupt Enable Set
36.10.6. Interrupt Flag Status and Clear
36.10.7. Status
36.10.8. Synchronization Busy
36.10.9. Address
36.10.10. Data
36.10.11. Debug Control
37. TC – Timer/Counter
37.1. Overview
37.2. Features
37.3. Block Diagram
37.4. Signal Description
37.5. Product Dependencies
37.5.1. I/O Lines
37.5.2. Power Management
37.5.3. Clocks
37.5.4. DMA
37.5.5. Interrupts
37.5.6. Events
37.5.7. Debug Operation
37.5.8. Register Access Protection
37.5.9. Analog Connections
37.6. Functional Description
37.6.1. Principle of Operation
37.6.2. Basic Operation
37.6.2.1. Initialization
37.6.2.2. Enabling, Disabling, and Resetting
37.6.2.3. Prescaler Selection
37.6.2.4. Counter Mode
37.6.2.5. Counter Operations
37.6.2.6. Compare Operations
37.6.2.7. Double Buffering
37.6.2.8. Capture Operations
37.6.3. Additional Features
37.6.3.1. One-Shot Operation
37.6.3.2. Time-Stamp Capture
37.6.3.3. Minimum Capture
37.6.3.4. Maximum Capture
37.6.4. DMA Operation
37.6.5. Interrupts
37.6.6. Events
37.6.7. Sleep Mode Operation
37.6.8. Synchronization
37.7. Register Description
37.7.1. Register Summary - 8-bit Mode
37.7.1.1. Control A
37.7.1.2. Control B Clear
37.7.1.3. Control B Set
37.7.1.4. Event Control
37.7.1.5. Interrupt Enable Clear
37.7.1.6. Interrupt Enable Set
37.7.1.7. Interrupt Flag Status and Clear
37.7.1.8. Status
37.7.1.9. Waveform Generation Control
37.7.1.10. Driver Control
37.7.1.11. Debug Control
37.7.1.12. Synchronization Busy
37.7.1.13. Counter Value, 8-bit Mode
37.7.1.14. Period Value, 8-bit Mode
37.7.1.15. Channel x Compare/Capture Value, 8-bit Mode
37.7.1.16. Period Buffer Value, 8-bit Mode
37.7.1.17. Channel x Compare Buffer Value, 8-bit Mode
37.7.2. Register Summary - 16-bit Mode
37.7.2.1. Control A
37.7.2.2. Control B Clear
37.7.2.3. Control B Set
37.7.2.4. Event Control
37.7.2.5. Interrupt Enable Clear
37.7.2.6. Interrupt Enable Set
37.7.2.7. Interrupt Flag Status and Clear
37.7.2.8. Status
37.7.2.9. Waveform Generation Control
37.7.2.10. Driver Control
37.7.2.11. Debug Control
37.7.2.12. Synchronization Busy
37.7.2.13. Counter Value, 16-bit Mode
37.7.2.14. Channel x Compare/Capture Value, 16-bit Mode
37.7.2.15. Channel x Compare Buffer Value, 16-bit Mode
37.7.3. Register Summary - 32-bit Mode
37.7.3.1. Control A
37.7.3.2. Control B Clear
37.7.3.3. Control B Set
37.7.3.4. Event Control
37.7.3.5. Interrupt Enable Clear
37.7.3.6. Interrupt Enable Set
37.7.3.7. Interrupt Flag Status and Clear
37.7.3.8. Status
37.7.3.9. Waveform Generation Control
37.7.3.10. Driver Control
37.7.3.11. Debug Control
37.7.3.12. Synchronization Busy
37.7.3.13. Counter Value, 32-bit Mode
37.7.3.14. Channel x Compare/Capture Value, 32-bit Mode
37.7.3.15. Channel x Compare Buffer Value, 32-bit Mode
38. TCC – Timer/Counter for Control Applications
38.1. Overview
38.2. Features
38.3. Block Diagram
38.4. Signal Description
38.5. Product Dependencies
38.5.1. I/O Lines
38.5.2. Power Management
38.5.3. Clocks
38.5.4. DMA
38.5.5. Interrupts
38.5.6. Events
38.5.7. Debug Operation
38.5.8. Register Access Protection
38.5.9. Analog Connections
38.6. Functional Description
38.6.1. Principle of Operation
38.6.2. Basic Operation
38.6.2.1. Initialization
38.6.2.2. Enabling, Disabling, and Resetting
38.6.2.3. Prescaler Selection
38.6.2.4. Counter Operation
38.6.2.5. Compare Operations
38.6.2.6. Double Buffering
38.6.2.7. Capture Operations
38.6.3. Additional Features
38.6.3.1. One-Shot Operation
38.6.3.2. Circular Buffer
38.6.3.3. Dithering Operation
38.6.3.4. Ramp Operations
38.6.3.5. Recoverable Faults
38.6.3.6. Non-Recoverable Faults
38.6.3.7. Time-Stamp Capture
38.6.3.8. Waveform Extension
38.6.3.9. WaveformGenerationinRAMP1modeWithRestartAction
38.6.4. Master/Slave Operation
38.6.5. DMA, Interrupts, and Events
38.6.5.1. DMA Operation
38.6.5.2. Interrupts
38.6.5.3. Events
38.6.6. Sleep Mode Operation
38.6.7. Synchronization
38.7. Register Summary
38.8. Register Description
38.8.1. Control A
38.8.2. Control B Clear
38.8.3. Control B Set
38.8.4. Synchronization Busy
38.8.5. Fault Control A and B
38.8.6. Waveform Extension Control
38.8.7. Driver Control
38.8.8. Debug control
38.8.9. Event Control
38.8.10. Interrupt Enable Clear
38.8.11. Interrupt Enable Set
38.8.12. Interrupt Flag Status and Clear
38.8.13. Status
38.8.14. Counter Value
38.8.15. Pattern
38.8.16. Waveform
38.8.17. Period Value
38.8.18. Compare/Capture Channel x
38.8.19. Pattern Buffer
38.8.20. Waveform Buffer
38.8.21. Period Buffer Value
38.8.22. Channel x Compare/Capture Buffer Value
39. TRNG – True Random Number Generator
39.1. Overview
39.2. Features
39.3. Block Diagram
39.4. Signal Description
39.5. Product Dependencies
39.5.1. I/O Lines
39.5.2. Power Management
39.5.3. Clocks
39.5.4. DMA
39.5.5. Interrupts
39.5.6. Events
39.5.7. Debug Operation
39.5.8. Register Access Protection
39.5.9. Analog Connections
39.6. Functional Description
39.6.1. Principle of Operation
39.6.2. Basic Operation
39.6.2.1. Initialization
39.6.2.2. Enabling, Disabling and Resetting
39.6.3. Interrupts
39.6.4. Events
39.6.5. Sleep Mode Operation
39.6.6. Synchronization
39.7. Register Summary
39.8. Register Description
39.8.1. Control A
39.8.2. Event Control
39.8.3. Interrupt Enable Clear
39.8.4. Interrupt Enable Set
39.8.5. Interrupt Flag Status and Clear
39.8.6. Output Data
40. AES – Advanced Encryption Standard
40.1. Overview
40.2. Features
40.3. Block Diagram
40.4. Signal Description
40.5. Product Dependencies
40.5.1. I/O Lines
40.5.2. Power Management
40.5.3. Clocks
40.5.4. DMA
40.5.5. Interrupts
40.5.6. Events
40.5.7. Debug Operation
40.5.8. Register Access Protection
40.5.9. Analog Connections
40.6. Functional Description
40.6.1. Principle of Operation
40.6.2. Basic Operation
40.6.2.1. Initialization
40.6.2.2. Enabling, Disabling, and Resetting
40.6.2.3. Basic Programming
40.6.2.4. Start Modes
40.6.2.5. Computation of last Nk words of expanded key
40.6.2.6. Hardware Countermeasures against Differential Power Analysis Attacks
40.6.3. Galois Counter Mode (GCM)
40.6.3.1. GCM Operation
40.6.4. Synchronization
40.7. Register Summary
40.8. Register Description
40.8.1. Control A
40.8.2. Control B
40.8.3. Interrupt Enable Clear
40.8.4. Interrupt Enable Set
40.8.5. Interrupt Flag Status and Clear
40.8.6. Data Buffer Pointer
40.8.7. Debug
40.8.8. Keyword
40.8.9. Data
40.8.10. Initialization Vector Register
40.8.11. Hash Key (GCM mode only)
40.8.12. Galois Hash (GCM mode only)
40.8.13. Galois Hash x (GCM mode only)
40.8.14. Random Seed
41. USB – Universal Serial Bus
41.1. Overview
41.2. Features
41.3. USB Block Diagram
41.4. Signal Description
41.5. Product Dependencies
41.5.1. I/O Lines
41.5.2. Power Management
41.5.3. Clocks
41.5.4. DMA
41.5.5. Interrupts
41.5.6. Events
41.5.7. Debug Operation
41.5.8. Register Access Protection
41.5.9. Analog Connections
41.5.10. Calibration
41.6. Functional Description
41.6.1. USB General Operation
41.6.1.1. Initialization
41.6.2. USB Device Operations
41.6.2.1. Initialization
41.6.2.2. Endpoint Configuration
41.6.2.3. Multi-Packet Transfers
41.6.2.4. USB Reset
41.6.2.5. Start-of-Frame
41.6.2.6. Management of SETUP Transactions
41.6.2.7. Management of OUT Transactions
41.6.2.8. Multi-Packet Transfers for OUT Endpoint
41.6.2.9. Management of IN Transactions
41.6.2.10. Multi-Packet Transfers for IN Endpoint
41.6.2.11. Ping-Pong Operation
41.6.2.12. Feedback Operation
41.6.2.13. Suspend State and Pad Behavior
41.6.2.14. Remote Wakeup
41.6.2.15. Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Device
41.6.2.16. USB Device Interrupt
41.6.3. Host Operations
41.6.3.1. Device Detection and Disconnection
41.6.3.2. Host Terminology
41.6.3.3. USB Reset
41.6.3.4. Pipe Configuration
41.6.3.5. Pipe Activation
41.6.3.6. Pipe Address Setup
41.6.3.7. Suspend and Wakeup
41.6.3.8. Phase-locked SOFs
41.6.3.9. Management of Control Pipes
41.6.3.10. Management of IN Pipes
41.6.3.11. Management of OUT Pipes
41.6.3.12. Alternate Pipe
41.6.3.13. Data Flow Error
41.6.3.14. CRC Error
41.6.3.15. PERR Error
41.6.3.16. Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Host.
41.6.3.17. Host Interrupt
41.7. Communication Device Host Register Summary
41.8. Communication Device Host Register Description
41.8.1. Control A
41.8.2. Synchronization Busy
41.8.3. QOS Control
41.8.4. Finite State Machine Status
41.8.5. Descriptor Address
41.8.6. Pad Calibration
41.9. Device Registers - Common -Register Summary
41.10. Device Registers - Common
41.10.1. Control B
41.10.2. Device Address
41.10.3. Status
41.10.4. Device Frame Number
41.10.5. Device Interrupt Enable Clear
41.10.6. Device Interrupt Enable Set
41.10.7. Device Interrupt Flag Status and Clear
41.10.8. Endpoint Interrupt Summary
41.11. Device Endpoint Register Summary
41.12. Device Endpoint Register Description
41.12.1. Device Endpoint Configuration register n
41.12.2. EndPoint Status Clear n
41.12.3. EndPoint Status Set n
41.12.4. EndPoint Status n
41.12.5. Device EndPoint Interrupt Flag n
41.12.6. Device EndPoint Interrupt Enable n
41.12.7. Device Interrupt EndPoint Set n
41.13. Endpoint Descriptor Structure
41.14. Device Endpoint RAM Register Summary
41.15. Device Endpoint RAM Register Description
41.15.1. Address of Data Buffer
41.15.2. Packet Size
41.15.3. Extended Register
41.15.4. Device Status Bank
41.16. Host Registers - Common - Register Summary
41.17. Host Registers - Common - Register Description
41.17.1. Control B
41.17.2. Host Start-of-Frame Control
41.17.3. Status
41.17.4. Host Frame Number
41.17.5. Host Frame Length
41.17.6. Host Interrupt Enable Register Clear
41.17.7. Host Interrupt Enable Register Set
41.17.8. Host Interrupt Flag Status and Clear
41.17.9. Pipe Interrupt Summary
41.18. Host Registers - Pipe - Register Summary
41.19. Host Registers - Pipe - Register Description
41.19.1. Host Pipe n Configuration
41.19.2. Interval for the Bulk-Out/Ping Transaction
41.19.3. Pipe Status Clear n
41.19.4. Pipe Status Set Register n
41.19.5. Pipe Status Register n
41.19.6. Host Pipe Interrupt Flag Register
41.19.7. Host Pipe Interrupt Clear Register
41.19.8. Host Interrupt Pipe Set Register
41.20. Pipe Descriptor Structure
41.21. Host Registers - Pipe RAM - Register Summary
41.22. Host Registers - Pipe RAM - Register Description
41.22.1. Address of the Data Buffer
41.22.2. Packet Size
41.22.3. Extended Register
41.22.4. Host Status Bank
41.22.5. Host Control Pipe
41.22.6. Host Status Pipe
42. CCL – Configurable Custom Logic
42.1. Overview
42.2. Features
42.3. Block Diagram
42.4. Signal Description
42.5. Product Dependencies
42.5.1. I/O Lines
42.5.2. Power Management
42.5.3. Clocks
42.5.4. DMA
42.5.5. Interrupts
42.5.6. Events
42.5.7. Debug Operation
42.5.8. Register Access Protection
42.5.9. Analog Connections
42.6. Functional Description
42.6.1. Principle of Operation
42.6.2. Operation
42.6.2.1. Initialization
42.6.2.2. Enabling, Disabling, and Resetting
42.6.2.3. Lookup Table Logic
42.6.2.4. Truth Table Inputs Selection
42.6.2.5. Filter
42.6.2.6. Edge Detector
42.6.2.7. Sequential Logic
42.6.3. Events
42.6.4. Sleep Mode Operation
42.7. Register Summary
42.8. Register Description
42.8.1. Control
42.8.2. Sequential Control x
42.8.3. LUT Control x
43. Operational Amplifier Controller (OPAMP)
43.1. Overview
43.2. Features
43.3. Block Diagram
43.4. Signal Description
43.5. Product Dependencies
43.5.1. I/O Lines
43.5.2. Power Management
43.5.3. Clocks
43.5.4. DMA
43.5.5. Interrupts
43.5.6. Events
43.5.7. Debug Operation
43.5.8. Register Access Protection
43.5.9. Analog Connections
43.5.10. Other dependencies
43.6. Functional Description
43.6.1. Principle of Operation
43.6.2. Basic Operation
43.6.2.1. Initialization
43.6.2.2. Enabling, Disabling, and Resetting
43.6.3. DMA Operation
43.6.4. Interrupts
43.6.5. Events
43.6.6. Sleep Mode Operation
43.6.7. Synchronization
43.6.8. Configuring the Operational Amplifiers
43.6.9. Standalone Mode
43.6.10. Built-in Modes
43.6.10.1. Voltage Follower
43.6.10.2. Inverting PGA
43.6.10.3. Non-Inverting PGA
43.6.10.4. Cascaded Inverting PGA
43.6.10.5. Cascaded Non-Inverting PGA
43.6.10.6. Two OPAMPs Differential Amplifier
43.6.10.7. Instrumentation Amplifier
43.6.10.8. Transimpedance amplifier
43.6.10.9. Programmable Hysteresis
43.6.11. ADC Driver
43.6.11.1. Buffer/PGA for ADC
43.6.11.2. Offset and Gain Compensation
43.6.11.3. Offset Compensation
43.6.11.4. Gain Compensation
43.6.12. AC Driver
43.6.13. Input Connection to DAC
43.6.14. Voltage Doubler
43.6.15. Performance vs. Power Consumption
43.7. Register Summary
43.8. Register Description
43.8.1. Control A
43.8.2. Status
43.8.3. OPAMP Control x
44. ADC – Analog-to-Digital Converter
44.1. Overview
44.2. Features
44.3. Block Diagram
44.4. Signal Description
44.5. Product Dependencies
44.5.1. I/O Lines
44.5.2. Power Management
44.5.3. Clocks
44.5.4. DMA
44.5.5. Interrupts
44.5.6. Events
44.5.7. Debug Operation
44.5.8. Register Access Protection
44.5.9. Analog Connections
44.5.10. Calibration
44.6. Functional Description
44.6.1. Principle of Operation
44.6.2. Basic Operation
44.6.2.1. Initialization
44.6.2.2. Enabling, Disabling and Resetting
44.6.2.3. Operation
44.6.2.4. Prescaler Selection
44.6.2.5. Reference Configuration
44.6.2.6. ADC Resolution
44.6.2.7. Differential and Single-Ended Conversions
44.6.2.8. Conversion Timing and Sampling Rate
44.6.2.9. Accumulation
44.6.2.10. Averaging
44.6.2.11. Oversampling and Decimation
44.6.2.12. Automatic Sequences
44.6.2.13. Window Monitor
44.6.2.14. Offset and Gain Correction
44.6.3. Additional Features
44.6.3.1. Double Buffering
44.6.3.2. Device Temperature Measurement
44.6.4. DMA Operation
44.6.5. Interrupts
44.6.6. Events
44.6.7. Sleep Mode Operation
44.6.8. Synchronization
44.7. Register Summary
44.8. Register Description
44.8.1. Control A
44.8.2. Control B
44.8.3. Reference Control
44.8.4. Event Control
44.8.5. Interrupt Enable Clear
44.8.6. Interrupt Enable Set
44.8.7. Interrupt Flag Status and Clear
44.8.8. Sequence Status
44.8.9. Input Control
44.8.10. Control C
44.8.11. Average Control
44.8.12. Sampling Time Control
44.8.13. Window Monitor Lower Threshold
44.8.14. Window Monitor Upper Threshold
44.8.15. Gain Correction
44.8.16. Offset Correction
44.8.17. Software Trigger
44.8.18. Debug Control
44.8.19. Synchronization Busy
44.8.20. Result
44.8.21. Sequence Control
44.8.22. Calibration
45. AC – Analog Comparators
45.1. Overview
45.2. Features
45.3. Block Diagram
45.4. Signal Description
45.5. Product Dependencies
45.5.1. I/O Lines
45.5.2. Power Management
45.5.3. Clocks
45.5.4. DMA
45.5.5. Interrupts
45.5.6. Events
45.5.7. Debug Operation
45.5.8. Register Access Protection
45.5.9. Analog Connections
45.6. Functional Description
45.6.1. Principle of Operation
45.6.2. Basic Operation
45.6.2.1. Initialization
45.6.2.2. Enabling, Disabling and Resetting
45.6.2.3. Comparator Configuration
45.6.2.4. Starting a Comparison
45.6.2.4.1. Continuous Measurement
45.6.2.4.2. Single-Shot
45.6.3. Selecting Comparator Inputs
45.6.4. Window Operation
45.6.5. VDD Scaler
45.6.6. Input Hysteresis
45.6.7. Propagation Delay vs. Power Consumption
45.6.8. Filtering
45.6.9. Comparator Output
45.6.10. Offset Compensation
45.6.11. DMA Operation
45.6.12. Interrupts
45.6.13. Events
45.6.14. Sleep Mode Operation
45.6.14.1. Continuous Measurement during Sleep
45.6.14.2. Single-Shot Measurement during Sleep
45.6.15. Synchronization
45.7. Register Summary
45.8. Register Description
45.8.1. Control A
45.8.2. Control B
45.8.3. Event Control
45.8.4. Interrupt Enable Clear
45.8.5. Interrupt Enable Set
45.8.6. Interrupt Flag Status and Clear
45.8.7. Status A
45.8.8. Status B
45.8.9. Debug Control
45.8.10. Window Control
45.8.11. Scaler n
45.8.12. Comparator Control n
45.8.13. Synchronization Busy
46. DAC – Digital-to-Analog Converter
46.1. Overview
46.2. Features
46.3. Block Diagram
46.4. Signal Description
46.5. Product Dependencies
46.5.1. I/O Lines
46.5.2. Power Management
46.5.3. Clocks
46.5.4. DMA
46.5.5. Interrupts
46.5.6. Events
46.5.7. Debug Operation
46.5.8. Register Access Protection
46.5.9. Analog Connections
46.6. Functional Description
46.6.1. Principle of Operation
46.6.2. Basic Operation
46.6.2.1. Initialization
46.6.2.2. Enabling, Disabling and Resetting
46.6.2.3. DAC Configuration
46.6.2.4. Digital to Analog Conversion
46.6.3. Additional Features
46.6.3.1. DAC0 as Internal Input
46.6.3.2. Output Buffer Current Control
46.6.3.3. Conversion Refresh
46.6.3.4. Differential Mode
46.6.3.5. Dithering Mode
46.6.4. Operating Conditions
46.6.5. DMA Operation
46.6.6. Interrupts
46.6.7. Events
46.6.8. Sleep Mode Operation
46.6.9. Synchronization
46.7. Register Summary
46.8. Register Description
46.8.1. Control A
46.8.2. Control B
46.8.3. Event Control
46.8.4. Interrupt Enable Clear
46.8.5. Interrupt Enable Set
46.8.6. Interrupt Flag Status and Clear
46.8.7. Status
46.8.8. Synchronization Busy
46.8.9. DAC0 Control
46.8.10. DAC1 Control
46.8.11. Data DAC0
46.8.12. Data DAC1
46.8.13. Data Buffer DAC0
46.8.14. Data Buffer DAC1
46.8.15. Debug Control
47. PTC - Peripheral Touch Controller
47.1. Overview
47.2. Features
47.3. Block Diagram
47.4. Signal Description
47.5. Product Dependencies
47.5.1. I/O Lines
47.5.1.1. Mutual-Capacitance Sensor Arrangement
47.5.1.2. Self-Capacitance Sensor Arrangement
47.5.2. Clocks
47.5.3. Analog-Digital Converter (ADC)
47.6. Functional Description
48. Electrical Characteristics
48.1. Disclaimer
48.2. Absolute Maximum Ratings
48.3. General Operating Ratings
48.4. Supply Characteristics
48.5. Maximum Clock Frequencies
48.6. Power Consumption
48.7. Wake-Up Time
48.8. I/O Pin Characteristics
48.9. Injection Current
48.10. Analog Characteristics
48.10.1. Voltage Regulator Characteristics
48.10.1.1. Buck Converter
48.10.1.2. LDO Regulator
48.10.2. APWS
48.10.3. Power-On Reset (POR) Characteristics
48.10.4. Brown-Out Detectors (BOD) Characteristics
48.10.5. Analog-to-Digital Converter (ADC) Characteristics
48.10.6. Digital to Analog Converter (DAC) Characteristics
48.10.7. Analog Comparator (AC) Characteristics
48.10.8. DETREF
48.10.9. Temperature Sensor Characteristics
48.10.10. OPAMP
48.11. NVM Characteristics
48.12. Oscillators Characteristics
48.12.1. Crystal Oscillator (XOSC) Characteristics
48.12.2. External 32KHz Crystal Oscillator (XOSC32K) Characteristics
48.12.3. 32.768kHz Internal Oscillator (OSC32K) Characteristics
48.12.4. Internal Ultra Low Power 32KHz RC Oscillator (OSCULP32K) Characteristics
48.12.5. Digital Frequency Locked Loop (DFLL48M) Characteristics
48.12.6. 16MHz RC Oscillator (OSC16M) Characteristics
48.12.7. Digital Phase Lock Loop (DPLL) Characteristics
48.13. Timing Characteristics
48.13.1. External Reset Pin
48.13.2. SERCOM in SPI Mode in PL0
48.13.3. SERCOM in SPI Mode in PL2
48.14. USB Characteristics
49. Electrical Characteristics - Extended Temperature Range 105°C
49.1. Disclaimer
49.2. General Operating Ratings - 105°C
49.3. Power Consumption
49.4. I/O Pin Characteristics
49.5. Injection Current - 105°C
49.6. Analog Characteristics
49.6.1. Power-On Reset (POR) Characteristics - 105°C
49.6.2. Brown-Out Detectors (BOD) Characteristics - 105°C
49.6.3. Digital to Analog Converter (DAC) Characteristics - 105°C
49.6.4. Analog Comparator (AC) Characteristics
49.6.5. DETREF - 105°C
49.6.6. Temperature Sensor Characteristics - 105°C
49.6.7. OPAMP
49.7. NVM Characteristics
49.8. Oscillators Characteristics
49.8.1. Crystal Oscillator (XOSC) Characteristics
49.8.2. External 32KHz Crystal Oscillator (XOSC32K) Characteristics - 105°C
49.8.3. 32.768kHz Internal Oscillator (OSC32K) Characteristics - 105°C
49.8.4. Internal Ultra Low Power 32KHz RC Oscillator (OSCULP32K) Characteristics - 105°C
49.8.5. 16MHz RC Oscillator (OSC16M) Characteristics - 105°C
49.8.6. Digital Frequency Locked Loop (DFLL48M) Characteristics - 105°C
49.8.7. Digital Phase Lock Loop (DPLL) Characteristics - 105°C
49.9. Timing Characteristics
49.9.1. SERCOM in SPI Mode in PL2 - 105°C
50. Typical Characteristics
50.1. Power Consumption over Temperature in Sleep Modes
51. Appendix A
51.1. SIL 2-Enabled Functional Safety Devices
51.1.1. Ordering Information
52. Packaging Information
52.1. Thermal Considerations
52.1.1. Thermal Resistance Data
52.1.2. Junction Temperature
52.2. Package Drawings
52.2.1. 64-Ball WLCSP
52.2.2. 64 pin TQFP
52.2.3. 64 pin QFN
52.2.4. 48 pin TQFP
52.2.5. 48 pin QFN
52.2.6. 32 pin TQFP
52.2.7. 32 pin QFN
52.3. Soldering Profile
53. Schematic Checklist
53.1. Introduction
53.1.1. Operation in Noisy Environment
53.2. Power Supply
53.2.1. Power Supply Connections
53.2.2. Special Considerations for QFN Packages
53.3. External Analog Reference Connections
53.4. External Reset Circuit
53.5. Unused or Unconnected Pins
53.6. Clocks and Crystal Oscillators
53.6.1. External Clock Source
53.6.2. Crystal Oscillator
53.6.3. External Real Time Oscillator
53.6.4. Calculating the Correct Crystal Decoupling Capacitor
53.7. Programming and Debug Ports
53.7.1. Cortex Debug Connector (10-pin)
53.7.2. 10-pin JTAGICE3 Compatible Serial Wire Debug Interface
53.7.3. 20-pin IDC JTAG Connector
53.8. USB Interface
54. Conventions
54.1. Numerical Notation
54.2. Memory Size and Type
54.3. Frequency and Time
54.4. Registers and Bits
55. Acronyms and Abbreviations
56. Datasheet Revision History
56.1. Rev. C - 03/2020
56.2. Rev B - 02/2020
56.3. Rev. A - 02/2017
56.4. Rev J - 06/2016
56.5. Rev I - 02/2016
56.6. Rev H - 12/2015
56.7. Rev G - 11/2015
56.8. Rev F - 09/2015
56.9. Rev E - 07/2015
56.10. Rev D - 06/2015
56.11. Rev C - 03/2015
56.12. Rev B - 02/2015
56.13. Rev A - 01/2015
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