Revision History

The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

Revision	Date	Description
C	01/2022	The following is a summary of changes made in this revision. Updated Power Supply Sequencing. Updated I/O Glitch During Power-Up and I/O Glitch During Power-Down.
B	11/2021	The following is a summary of changes made in this revision. Replaced “slew rate” with “ramp time” in Reset Circuit for the DEVRST_N introduction. Reprashed the table titles as “Unused Bank Supplies” in Unused Pin Configurations for more clarity. Updated the footnote of tables Table 1 to Table 4 for clarity.
A	09/2021	The following is a summary of changes made in this revision. Document name prefix was changed from AC393 to AN4153. Document number was changed from 51900393 to DS00004153. Added more information in I/O Glitch at Auto-Update During POR. Updated termination information for probe I/Os, see Table 1. Reorganized and updated the earlier “section 2.4 Limiting Surge Current During Device Reset” to Limiting VDD Surge Current. Corrected table numbering from Table 14 to Table 4 in Brownout Detection (BOD). Added Appendix E: X-Ray Inspection.
15.0	10/2020	The following is a summary of changes made in this revision. Renamed Table 1 to Table 4 as “Requirements for Bank Supplies”. Information about I/O glitch at auto-update during POR was added, see I/O Glitch at Auto-Update During POR. Updated the note in Power Supplies to include Aux. PLL PCIe Supply in the power supply settings description for PLLs. Internal pull-up clamp diode is not present in MSIO. Hence, removed MSIO from Figure 1. In Table 1 (Design Checklist → Power Supplies → VDDI Bank Supplies), added reference to Table 1 to Table 4 for verifying the requirements for VDDI Bank supplies. Updated the pull-down resistor requirement to 150 Ω for the xDDR_IMP_CALIB_ECC pin of LPDDR and DDR2 interface. See Figure 1 and Figure 2.
14.0	—	The following is a summary of changes made in revision 14.0 of this document. Information about I/O glitches during power-up, power-down, and on blank devices was updated. For more information, see I/O Glitch. A figure was added to illustrate SPI master mode programming. For more information, see SPI Master Programming Information about simultaneous switching noise support was added. For more information, see Simultaneous Switching Noise. The design checklist from CL0034: SmartFusion2/IGLOO2 Hardware Board Design Checklist was merged into this document. List of device-package combinations that do not have SERDES_x_VDD pins was added. For more information, see Table 1. Design checklist was added in Board Design and Layout Checklist. Information about the de-coupling capacitor and SmartFusion2/IGLOO2 placement was added in Component Placement. Figures were updated in LPDDR and DDR2 Design and DDR3 Guidelines.
13.0	—	The following is a summary of changes made in revision 13.0 of this document. Updated Figure 1, Figure 1, Figure 2, Figure 1, and Figure 2. Updated Table 1, Table 2, Table 3, Table 4, and Table 1. AC408: Creating Schematic Symbols using Cadence OrCAD Capture CIS for SmartFusion2 and IGLOO2 Designs is merged with this document.
12.0	—	The following is a summary of changes made in revision 12.0 of this document. Recommended bank supplies are updated for the FG484 package. See Table 2. Recommended bank supplies are updated for VF400 and FCS325 Packages. See Table 3. Recommended bank supplies are updated for VF256 and TQ144 Packages. See Table 4. Added a note about DQ pins that all 4- and 8-bit pins are interchangeable in LPDDR, DDR2, and DDR3 memories. See Figure 1. Added that the SERDES_x_L[01/23]_VDDAPLL pin supports only 2.5 V, and removed 1.2 V references from all occurrences. For more information, see figure 1 and Table 4. AC394: Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design was added as a part of Board Design guidelines itself.
11.0	—	The following is a summary of changes made in revision 11.0 of this document. The filter circuit for SERDES_x_VDD was removed. Even if it was used in the board design previously, it does not affect the functionality of the board. See Figure 1. Information about VDDI2 was updated. See Table 3 and Table 4. Information about reset circuit was updated. see Reset Circuit. Changed the document to the new template.
10.0	—	The following is a summary of the changes made in revision 10.0 of this document. Updated Power Supplies (SAR 77745 and SAR 79670). Updated Table 1 (SAR 78887). Updated SPI Master Programming (SAR 75910). Updated SerDes (SAR 78504). Updated User I/O and Clock Pins (SAR 61314).
9.0	—	The following is a summary of the changes made in revision 9.0 of this document. Updated Figure 1 (SAR 72533). Added CCC_PLL_VDDA and MSS_xDDR_PLL_VDDA details under Power Supplies (SAR 72533). Deleted the RC Values for Filter Circuitry table (SAR 72533). Added the M2S060T/M2GL060T device column in Table 4(SAR 70484).
8.0	—	The following is a summary of the changes made in revision 8.0 of this document. Updated Figure 1 (SAR 66682). Updated the RC Values for Filter Circuitry table (SAR 66682 and SAR 65367). Updated Table 1 (SAR 70545). Updated Table 4 (SAR 67599). Updated Table 1 to replace pin SC_SPI_SS with SC_SPI_SDO. Updated PLL Filter (SAR 60798). Updated Figure 1 (SAR 65438, SAR 69743 and SAR 69580). Updated Figure 2 (SAR 65438). Updated Figure 2 (SAR 65438). Added Figure 1 (SAR 64377).
7.0	—	The following is a summary of the changes made in revision 7.0 of this document. Updated Figure 1 and Figure 1 (SAR 62858). Updated Power Supply Sequencing(SAR 64117). Updated Power Supply Flow. Added Table 4. Updated Table 1, Table 1, and Table 1 (SAR 62858). Updated AC Coupling. Updated Reset Circuit. Updated Figure 1, Figure 2, Figure 1, and Figure 2 (SAR 65438). Replaced all instances of VQ144 with TQ144 Package. Removed all instances of and references to M2S100 and M2GL100 device (SAR 62858).
6.0	—	The following is a summary of the changes made in revision 6.0 of this document. Updated Design Considerations (SAR 58055). Updated Power Supplies (SAR 52580). Updated Power Supply Sequencing (SAR 59593 and SAR 57004). Updated Figure 1 (SAR 52580). Added M2S090T/M2GL090T-FCS325 information for power supplies in Table 1 (SAR 58241). Added a foot note to Table 1(SAR 59563). Updated SerDes Reference Clock Requirements (SAR 60213). Updated Table 1 (SAR 58085). Updated Figure 1 (SAR 56598). Added a foot note to Table 1 (SAR 59563). Updates were made to maintain the style and consistency of the document.
5.0	—	The following is a summary of the changes made in revision 5.0 of this document. Updated Power Supply Sequencing, Figure 1, Figure 1, and Table 1 (SAR 52580). Updated main crystal oscillator pins naming convention (SAR 53177). Updated Table 1 (SAR 55659). Updated Figure 1, Figure 2, Figure 1, and Figure 2(SAR 53161). Updated Table 1(SAR 53348).
4.0	—	The following is a summary of the changes made in revision 4.0 of this document. Corrected the ramp rate description to 50 μs in the Power Supply Sequencing (SAR 50245) (SAR 50844). Updated Figure 1 (SAR 50725). Added the Configuring Pins in Open Drain section.
3.0	—	The following is a summary of the changes made in revision 3.0 of this document. Updated the content for IGLOO2 devices (SAR 48630). Updated Power Supply Sequencing. Updated DDR3 Guidelines. Updated the Temperature Sensing section.
2.0	—	The following is a summary of the changes made in revision 2.0 of this document. Modified the Unused Pin Configurations (SAR 47904). Updated Operating Voltage Rails (SAR 47548). Updated the Brownout Detection (BOD) (SAR 47904). Added Figure 1 (SAR 47904).
1.0	—	The following is a summary of the changes made in revision 1.0 of this document. Added the Power Supply Sequencing and Power-on Reset section (SAR 47223). Updated Figure 1 (previously figure 2) and added figure 4 (SAR 47223). Updated Table 1 and Table 1, and added Table 1 (SAR 47223).