LPDDR and DDR2 Design

The designer must be familiar with the specification and the basic electrical operation of the LPDDR/DDR2 interface. Data bus, data strobe, and data mask (byte enable) signals are point-to-point, whereas all other address, control, and clock signals are not point-to-point. The following figures show the connectivity of the SmartFusion2/IGLOO2 LPDDR interface and a 32-bit DDR2 interface respectively.

Figure 1. LPDDR Interface
  1. 1.Impedance calibration is optional for LPDDR operating in LVCMOS mode and is required for LPDDR1 operating in SSTL18 mode.
  2. 2.

    For a 4-bit or 8-bit DRAM, all DQ pins are interchangeable. All 4-bit and 8-bit DQ pins are interchangeable in LPDDR, DDR2, and DDR3 memories. For a 16-bit DRAM, DQ0 through DQ7 are interchangeable. Also, DQ8 through DQ15 are interchangeable. However, DQ0-7 pins or signals must not be interchanged with the DQ8-15 pins or signals.

  3. 3.

    Short ECC_TMATCH_ OUT and ECC_TMATCH_ IN when using ECC bits.

Figure 2. DDR2 Interface

With short traces, the address, control, and command signals might not require both parallel (RT) and series (RS) termination. In a worst-case scenario, a small series resistor (RS) of about 10 Ω or less is required. This series termination is not used for impedance matching, but for dampening the signals.

  1. 1.To get length matching, short the TMATCH_OUT to TMATCH_IN with the shortest loop.
  2. 2.Short ECC_TMATCH_ OUT and ECC_TMATCH_ IN when using ECC bits.