Reliability of DDR interface depends on the quality of the layout. There are many layout guidelines available from memory vendors. The following recommendations can also be used for routing the DDR3 signals. The following DDR3 signals are grouped.
Address/Command
Control
Clocks
The following table lists the signals that come under a particular group:
Group |
Signals |
|---|---|
Data |
DQ[0:7], DQ[8:15], DQ[16:23], DQ[24:31] and DQS[0:3], DM[0:3] |
Address/command |
A[0:15], BA[0:2], RAS#, CAS#, and WE# |
Control |
CS#, CKE, and ODT |
Clock |
CK and CK# |