I/O Glitch During Power-Down

I/O glitches can occur in some power-down sequences, and they can be ignored if good design practices are used.

To mitigate the I/O glitch:

  1. 1.Use any one of the following power-down sequence:
    1. a.Ensure that the DEVRST_N is kept de-asserted at 3.3 V while the power down of all the rails take place. DEVRST_N be asserted to 0 V only after all the rails are powered down.
    2. b.If possible, place the device in F*F mode prior to power-down. This also mitigates the glitches even if the DEVRSTn is asserted first or VPP is powered down first.
  2. 2.If power sequencing is not possible, add a 1 KΩ resistor to ground on all critical signal outputs like clocks and resets and other glitch sensitive I/Os.
Parent topic: I/O Glitch