Address, Control, Command, and Clock Routing

These signals must be routed in the fly-by topology and terminated with appropriate termination resistor at the end of the signals. The resistor termination must not have a stub longer than 600 mil.
The impedance for the trace depends on the stack-up and trace width. There are options to select the impedance based on the stack-up and trace width:
- 40 Ω impedance that needs wide traces (~7 to 8 mils). This gives the less cross talk and less spacing between the traces (~2x). Spacing between non DDR signals and DDR signals must be ~4x.
- 50 Ω impedance that requires smaller trace width (~4 to 6 mils). This needs more spacing between the traces (~3x). Spacing between non DDR signals and DDR signals must be ~4w to avoid crosstalk issues.
- Address and control signals can be referenced to a power plane if a ground plane is not available. The power plane must be related to the memory interface. However, a ground reference is preferred. Address and control signals must be kept on a different routing layer from DQ, DQS, and DM to isolate crosstalk between the signals.