PCB designers overlook the requirement of isolating the noise generated by the digital components with the SerDes high-speed designs. Provide a low-noise supply for the sensitive analog portions of the SerDes devices. Noise due to various power supply voltages can be coupled into the analog portion of the chip and may produce unwanted fluctuations in the sensitive stages of the device. The performance of SerDes depends on robust layout techniques. This section discusses the layout guidelines for power supply for the SerDes and the SerDes PLL.