Device Reset Induced VDD Surge Current

After device power-up, if the application asserts the DEVRST_N pin, a surge current on VDD may be observed. This section describes how to minimize additional surge current during the device reset operation. This additional surge current does not occur during device power-up; it is applicable only when DEVRST_N is asserted.

SmartFusion2/IGLOO2 device reset can be activated either directly through an external DEVRST_N pin or indirectly through the tamper macro IP. When the device reset is asserted, the system controller immediately puts the FPGA core in the inactive state, which induces a temporary current demand on VDD. This surge current is for a very short duration and is normally handled by bulk decoupling capacitors on the power plane in a typical system. In cases where Microchip-recommended board design guidelines cannot be implemented for decoupling capacitors for VDD (due to limited board spacing or other reasons), higher-than-expected surge current may occur during device reset.

The following table provides characterized surge current data for VDD during DEVRST_N assertion. This data represents the worst-case condition with no decoupling capacitors on the board.
Table 1. Surge Current on VDD during DEVRST_N Assertion (No Decoupling Capacitors on Board)
Device Width of Surge at 50% of Pulse (µS) Surge Current on VDD Units
0 °C to 85 °C –40 °C to 100 °C –55 °C to 125 °C
M2S005/M2GL005 2 0.5 0.6 0.6 A
M2S010/M2GL010 3 0.9 0.9 0.9 A
M2S025/M2GL025 6 1.7 1.7 1.7 A
M2S050/M2GL050 12 3.2 3.2 3.2 A
M2S060/M2GL060 12 3.2 3.2 3.2 A
M2S090/M2GL090 22 4.4 4.6 4.6 A
M2S150/M2GL150 42 7.0 7.3 7.3 A
The surge current data in the preceding table does not represent a typical system. To illustrate this, surge current during device reset was measured at room temperature separately for the M2S090 security evaluation kit and the M2S150 advanced development kit. These kits have decoupling capacitors according to the Microchip recommended board design guidelines. The following table lists the surge currents observed on the M2S090 security evaluation kit and the M2S150 advanced development kit. The surge current values were found to be within acceptable limits.
Table 2. M2S090 and M2S150 Surge Current During DEVRST_N Assertion (With Decoupling Capacitors on Board)
Kit Width of Surge at 50% of Pulse Surge Current
M2S090 Security Evaluation Kit 5 µs 150 mA
M2S150 Advanced Development Kit 40 µs 1.5 A
Note:
  1. 1.The amount of bulk capacitance placed for VDD was 1-100 µF, 3-220 µF, and 1-330 µF.
Parent topic: Limiting VDD Surge Current