On detection of a power-up event, the POR circuit sends the power-on reset signal to the system controller and reset controller in the SmartFusion2/IGLOO2 devices. The power-on reset circuitry in SmartFusion2/IGLOO2 devices require the VDD and VPP supplies to ramp monotonically from 0 V to the minimum recommended operating voltage within a predefined time. There is no sequencing requirement on VDD and VPP. Four ramp rate options are available during design generation: 50 µs, 1 ms, 10 ms, and 100 ms. Each selection represents the maximum ramp rate to apply to VDD and VPP. The ramp rates can be configured by using the Libero software.
The SERDES_VDD pins are shorted to VDD on silicon die; therefore, Microchip recommends using the same regulator to power up the VDD, SERDES_VDD and SERDES_VDDAIO pins. These three voltage supplies must be powered at the same voltage and must be ramped up and ramped down at the same time.
For information about the power-up to functional time sequence, see DS0128: IGLOO2 and SmartFusion2 Datasheet.
For power-down, if no external device (such as brownout detection or POR reset chip) is used to drive the DEVRSTn pin, it is recommended to power-down VPP before any other rail. If an external brownout detection or a reset device drives DEVRSTn where DEVRSTn is asserted and if any of the FPGA rails fall below the recommended operating conditions, no specific power-down sequence is required.
Use of an external brownout detection or a reset device to assert the DEVRSTn pin is strongly recommended when any of the FPGA supplies are below the recommended operating condition. For more information about this implementation, see Brownout Detection (BOD).