SerDes Reference Clock Requirements

The selection of the reference clock source or clock oscillator is driven by many parameters such as frequency range, output voltage swing, jitter (deterministic, random, and peak-to-peak), rise and fall times, supply voltage and current, noise specification, duty cycle and duty cycle tolerance, and frequency stability.

For SerDes reference clock pins, the internal ODT option must be enabled, and therefore, external termination is not required.

Following are the requirements for the SerDes reference clock:

See the PCI Express Base specification Rev 2.1 for detailed PHY specifications. Also see the PCIe Addin Card Electro-Mechanical (CEM) specifications.