PLL Filter

To obtain a reasonable level of long-term jitter, it is vital to supply the PLL with analog-grade power. An RC or RLC filter is used, where C is composed of multiple devices to obtain a wide spectrum of noise absorption. Although the circuit is simple, its effectiveness depends on specific board layout requirements. See Figure 1 for a typical power supply connection.

• The DC series resistance of this filter must be limited. Limit the voltage drop across this device to less than 5% under worst-case conditions.
• Place a main ceramic or tantalum capacitor (see Figure 1), in the filter design to obtain good low-frequency cut-off. At least one low equivalent series inductance (ESL) and low ESR capacitor in parallel (~0.1 μF ceramic capacitor in 0402 package) enables the filter to maintain its attenuation through moderately high frequencies.

• The package ball grid array (BGA) pattern allows the placement of 0402 or 0201 components across the SERDES_x_Lyz_VDDAPLL and SERDES_x_Lyz_REFRET pins on the backside of the board.

• For the SerDes block, SERDES_x_Lyz_REFRET serves as the local on-chip ground return path for SERDES_x_Lyz_VDDAPLL. Therefore, the external board ground must not get shorted with SERDES_x_Lyz_REFRET under any circumstances.

• High-quality series inductors must not be used without a series resistor when there is a high-gain series resonator. Avoid using inductive chokes in any supply path unless care is taken to manage resonance.

See Figure 1 for SerDes analog power connections. A high-precision 1.2 KΩ, 1% resistor in either a 0402 or 0201 package is required for the external reference resistor connected between SERDES_x_Lyz_REXT and SERDES_x_Lyz_REFRET.