Traces must not be routed at the edge of the reference plane and over via anti pads.
When routing the data signals, the longest signals must be routed first, this allows to adjust the length for the short length signals, when routing data signals.
Serpentine routing must be used to adjust the data group signals to meet this requirement.
The DQS signal must be routed along with associated data byte lane on the same critical layer with the same via count. Using more than three vias in the connection between the FPGA controller and memory device must be avoided.
The impedance for the data traces depends on the stack-up and the trace width. There are options to select the impedance based on the stack-up and trace width.
50 Ω impedance, which requires smaller trace width (~4 to 6 mils). This requires more spacing between the traces (~3x). Spacing between non DDR signals and DDR signals must be ~4x.
All data lanes must be matched to within 0.5 inch.
Within the data lane, each trace must be matched to within ±10mils of its respective data strobe
The DQS and DQS# need to be matched within ± 5mils.
Differential impedance must be between 75 to 100 Ω.
Differential traces adjacent to noisy signals or clock chips must be avoided.
Spacing between differential lines must be 5 to 8 mils.