Design Checklist

The following table lists the checks that design engineers must take care of while designing the system.

Table 1. Design Checklist
S.No. Checklist Yes/No

Read datasheet and pin description user guides:

2. Check for available designs and development tools.
3. See the board-level schematics of the SmartFusion2 Security Evaluation Kit or SmartFusion2 Advanced Development Kit.
Design Specifications
4. Draw the high-level design with architectural block diagram including all the basic interfaces.
5. Specify all the I/O interfaces for all banks in the FPGA.
6. Create a detailed functional verification test plan.
7. Check for IP software that impacts the system design.
Device Selection
8. Check for available device variants of the SmartFusion2 or IGLOO2 FPGA. Select a device based on the I/O pin count, transceivers, microcontroller subsystem (MSS) peripherals, phase-locked loops (PLLs), and speed grade.

Check device errata:

10. Compare the design requirements with the available interfaces and number of I/Os.
11. Estimate the required logic utilization, memory, number of I/O pins, and density.

Vertical Migration

If desiring pin compatibility within the same package, choose the largest density device for easy vertical migration without any pin conflict in case of future development.

For more information, see the application notes available under Schematics/PCB section.

13. Identify the clocking requirements.
14. Verify that the number of differential channels is adequate.

Power Analysis

Perform power analysis and check the results against the power budget. (Microchip Power Calculator can be used to analyze the power consumption. Estimate the dynamic and static power consumption, and ensure that the design does not violate the power budget.)


Noise Margin Analysis

Analyze the dynamic drive capability of output drivers to ensure that the drivers are not loaded beyond the limits (VOH, VOL, VIH, and VIL).

Loading Analysis

Analyze the dynamic drive capability of output drivers to confirm that the drivers are not loaded beyond the limits (CL)


Programming and Debugging Scheme

Check for the programming modes and the procedure to program the device. For programming or debugging through JTAG, add a 10-pin vertical header (2.54 mm pitch). For more information about programming, see IGLOO2 Programming User Guide and SmartFusion2 Programming User Guide.

Power Supply

Reference Documentation


Voltage Rails

The design can be created with just two voltage rails. See Obtaining a Two-Rail Design for Non-SerDes Applications.


VDD: Core Supply

VDD operates at 1.2 V.


VPP: Programming Supply

Charge pump and eNVM can operate at 2.5 V or 3.3 V.


VDDI Bank Supplies

Connect VDDI pins to support the I/O standards of each bank. Ensure I/O power pin compatibility with I/O standards. Check for the banks that must be powered even when unused. See Table 1 to Table 4. For recommendations on unused bank supplies, see Table 1. The recommendations vary from device to device.


SerDes Power Supplies

  • SERDES VDDAPLL to REFRET through resistor-capacitor (RC) filter circuitry (2.5 V)
  • SERDES PLL VDDA to PLL VSSA through RC filter circuitry - 2.5 V or 3.3 V


  • REFRET for the SerDes serves as the local on-chip ground return path for VDDAPLL. Therefore, external board ground must not short with REFRET under any circumstances.
  • A high precision 1.21K_1% Ù resistor is required to connect between REXT and REFRET.

For detailed information about power supplies, see Figure 1.


If SERDES transceiver is not used, the pins need to be connected as follows:

  • SERDES VDDAPLL - 1.2 V or 2.5 V
  • SERDES PLL VDDA - 2.5 V or 3.3 V
  • SERDES PLL VSSA - Ground

VREF Power Supply

Design VREF pins to be noise free. VREF must be equal to half of VDDQ. See Figure 1.


Other Supplies

CCC PLL VDDA to PLL VSSA through RC filter circuitry- 2.5 V/ 3.3 V. DDR PLL VDDA to PLL VSSA through RC filter circuitry- 2.5 V/ 3.3 V. All PLL VDDA supplies must be tied to same supply source (either 2.5 V or 3.3 V). Using the Libero SoC software, a single supply can be selected globally.


Decoupling Capacitors

Perform power integrity (PI) analysis through the PI tool, and analyze the decoupling capacitor values and placement on the PCB.


Unused Condition

For unused conditions of power supply pins, see the corresponding pin assignment table available on the following pages:


Brownout Detection (BOD) Circuit

Ensure that brownout detection is implemented standalone or included as part of power management circuitry. See Brownout Detection (BOD).


Crystal Oscillators (External)

  • Main crystal oscillator
  • Auxiliary (RTC) crystal oscillator (not available in the M2S050T)

RC Oscillators (Internal)

  • 1-MHz RC oscillator
  • 50-MHz RC oscillator

IGLOO2 devices have only main crystal oscillator without auxiliary (RTC) crystal oscillator.

For more information about crystal oscillators, see Table 1.

FPGA Fabric Clock Sources

The input clock frequency range for fabric clock conditioning circuits (FABCCC) depends on the usage of PLL for output clock generation:

  • If the PLL is used, the PLL reference clock frequency must be between 1 MHz and 200 MHz.
  • If the PLL is bypassed, the FABCCC input clock frequency can be up to 400 MHz.

All CCC pins support external oscillators (differential or single ended).


Global buffer (GB) can be driven through dedicated global I/Os, CCC, or fabric (regular I/Os) routing.

The global network is composed of GBs to distribute low-skew clock signals or high-fanout nets.

Dedicated global I/Os drive the GBs directly and are the primary source for connecting external clock inputs (to minimize the delay) to the internal global clock network.

For more information, see UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide.


DEVRST_N – Input

The DEVRST_N pin must have a 10 KΩ pull-up resistor. The pin must not be left floating. If a push-button switch is used to generate reset, check for switch de-bounce. For more information about DEVRST_N, see Power Supply Flow.


In the JTAG interface, the VDDI bank supply must be powered up for programming. The following is a list of pins available for different activities:

  • JTAGSEL: Low (pull-down) > Arm Cortex-M3 JTAG; High (pull-up) > FPGA fabric JTAG.
  • TMS: Internal weak pull-up resistor.
  • TCK: External pin. must be pulled-down through 1 KΩ resistor. There is no internal pull-up resistor for this pin.
  • TDI: internal weak pull-up resistor.
  • TDO: no internal pull-up resistor.
  • TRSTB: internal weak pull-up resistor.

An FP4 or FP5 header (10 pin – 2.54 mm pitch) can be used to connect to FlashPro4 or FlashPro5.

For more information about JTAG, see Figure 1 and Table 1.


The device can be programmed either through JTAG interface or serial peripheral interface (SPI) interface.


If pulled low, it indicates that the device is to be re-programmed from an image in the external SPI flash attached through the SPI interface. If pulled high, the SPI is put in slave mode.

Add a 10kΩ external pull-up resistor to VDDI. Some devices do not support the FLASH_GOLDEN_N pin. Check the PPAT spreadsheets available on the following Microchip webpages:

For more information about dedicated pins including Flash_GOLDEN_N, see Table 1.

Configuring Pins in Open Drain Using Tri-state Buffer
35. To configure fabric pins in open-drain mode, the tristate buffer input pin must always be grounded, and the I/O pin of the FPGA must be connected to the active-low enable pin of the buffer. For more information, see Figure 1.  
SerDes Pins

Dedicated I/O are available for the SerDes high-speed serial interface, which supports the PCIe, SGMII, XAUI, and JESD204B protocols.

SERDES Clock: 100 MHz to 160 MHz LVDS source. The SerDes reference clock pins have internal on-die termination (ODT) settings. These settings can be enabled through the Libero software. The reference clock source (differential clock oscillator) is selected based on many parameters such as frequency range, output voltage swing, jitter (deterministic, random, and peak-to-peak), rise and fall times, supply voltage and current, noise specification, duty cycle, duty cycle tolerance, and frequency stability.

An example clock source can be the CCLD-033- LVDS clock oscillator. SerDes clock requirements for different protocols are as follows:

  • PCIe: 100 MHz
  • XAUI: 156.25 MHz
  • SGMII: 125 MHz
  • EPCS: 125 MHz

SerDes TXD: The transmit pair must alone have AC-coupling capacitors near the SmartFusion2/IGLOO2 device. AC-coupling capacitors of 75-200 nF are required for link detection. If the SerDes unit is unused, these pins must remain floating (DNC).

SerDes RXD: The receive pair must have AC-coupling capacitors near the endpoint device. If the SerDes unit unused, these pins must always be connected to ground.

For more information about SerDes, see SerDes.

DDR Interface

DDR Interface



VDDI bank supply must be powered as per the application:

  • For LPDDR - VDDI must be 1.8 V
  • For DDR2- VDDI must be 1.8 V
  • For DDR3- VDDI must be 1.5 V

DDR impedance calibration pin must be pulled down with the following resistors:

  • For LPDDR- 150 Ω
  • For DDR2- 150 Ω
  • For DDR3- 240 Ω

Though calibration is not required, it is recommended to use corresponding resistor placeholder to connect the pin to the ground with or without a resistor. All data and data strobe signals have internal ODT settings, which can be enabled through the Libero software.

Hot-swapping and Cold-Sparing
38. All user I/Os have internal clamp diode control circuitry for protection. MSIO pins (except PCI 3.3 V standard) support the hot-swapping and coldsparing operations. MSIOD and DDRIO pins do not support hot swapping and cold-sparing operations  
General Guidelines
39. For all MSIO, MSIOD, and DDRIO, a weak internal pull-up resistor is available. In unused condition, these pins can be left floating.  
40. MSIOD and DDRIO support a maximum of 2.5 V. MSIO supports maximum of 3.3 V.  

There is one MSI special pin (MSIO) available that can be used as input only. This pin is differentially paired with FLASH_GOLDEN_N, which is always input only.

For more information, see the following documents:

42. One internal signal can be allocated for probing (for example, towards the oscilloscope feature). The two live probe I/O cells are dual-purpose. They can be used for the live probe functionality or used as user I/Os (MSIO).  
43. MSS peripherals (SPI, I2C, USB, and UART) are available.  
44. Provide pull-up resistors for all open-collector or open-drain pins, even if a pin is not used.  
45. Provide separate pull-down resistors for all used open-emitter or open-source pins.  
46. Enable internal pull-up/pull-down resistor option for all tristate nets through the Libero tool.  
47. Ensure that all the critical signals on the board are terminated properly.  
48. Terminate the unused interface signals properly to avoid metastability and electromagnetic interference (EMI)/electromagnetic compatibility (EMC) problems.  

Provide a sufficient number of ground pins for board-to-board connectors to ensure signal integrity (SI) across connectors.

Dense board-to-board connectors may cause severe cross-talk problems. The severity of crosstalk depends on the frequency of the signal and the spacing between signal pins on the connectors. (The number of ground pins may be obtained after performing SI analysis.) The severity can be reduced by providing ground pins between signal pins.

50. Use proper voltage-level translator devices for interfacing higher-operating voltage devices with lower-operating-voltage devices.  
51. Perform timing analysis of all components, taking into consideration the delays introduced by buffers in the data, address, or control paths.  
52. Perform signal integrity analysis (pre-layout and post-layout) for all critical interfaces and all types of I/Os using input/output buffer information specification (IBIS).  

Analyze the design for simultaneous switching noise (SSN) problems:

  • Use differential I/O standards and lower-voltage standards for high switching I/Os.
  • Reduce the number of simultaneously switching output pins within each bank.
  • Reduce the number of pins that switch voltage levels at the same time.
  • Use lower drive strengths for high switching I/Os. The default drive strength setting might be higher than the design requirement.
  • Spread output pins across multiple banks if possible.
  • If bank usage is substantially below 100%, spread the switching I/Os evenly throughout the bank to reduce the number of aggressors in a given area to reduce SSN.
  • Separate simultaneously switching pins from input pins that are susceptible to SSN.
54. Place important clock and asynchronous control signals near ground signals and away from large switching buses.  

I/O Pin Assignment

Use a spreadsheet to capture the list of design I/Os. Microchip provides detailed pinout information that can be downloaded from the website and customized to store the pinout information for specific designs. Pinout details for various packages with different densities are available on the following pages:

56. Check if there are any incompatible I/O standards combined in the same bank.  
57. Check if there are two interfaces with different voltage standards in the same bank.  
58. See the bank location diagrams in the IGLOO2 Pin Descriptions/SmartFusion2 Pin Descriptions documents to assess the preliminary placement of major components on PCB.