Even though SERDES0 and SERDES1 I/Os share the same power supply, make separate planes while connecting to the corresponding pins, as shown in the following figure. Each plane is separated as SERDES_0_L01_VDDAIO, SERDES_0_L23_VDDAIO, SERDES_1_L01_VDDAIO, and SERDES_1_L01_VDDAIO, as shown in the following figure. This reduces the noise coupling between the differential lanes.
Figure 1. Layout of SERDES_x_VDDAIO Plane
