Quad SPI DMA Driver

The Quad SPI Interface (QSPI) DMA driver provides a communication interface to operate a serial flash memory with DMA support.

User must configure DMAC system driver accordingly. The callback function is called when all the data is transferred or transfer error occurred, if it is registered via qspi_dma_register_callback function.

Summary of the API's Functional Features

The API provides functions to:

Initialize and deinitialize the driver and associated hardware
Enable or disable QSPI master
Hookup callback handlers on the data is transferred or transfer error occurred
Execute command in Serial Memory Mode

Summary of Configuration Options

Below is a list of the main QSPI parameters that can be configured in START. Many of these parameters are used by the qspi_dma_init function when initializing the driver and underlying hardware.

Select QSPI pins signals
Set QSPI baudrate
Select QSPI clock polarity and phase
Select QSPI DMA TX channel
Select QSPI DMA RX channel

Driver Implementation Description

The driver can be used for SPI serial memory middleware which support flash earse, program and read.

Example of Usage

The following shows a simple example of using the QSPI to send command to a serial memory flash. The callback function is called when the data is transferred.

The QSPI driver must have been initialized by qspi_dma_init. This initialization will configure the operation of the QSPI master.

          static uint8_t buf[16] = {0x0};
          static void xfer_complete_cb_QUAD_SPI_0(struct _dma_resource *resource)
          {
              /* Transfer completed */
          }
          /**
           * Example of using QUAD_SPI_0 to get N25Q256A status value,
           * and check bit 0 which indicate embedded operation is busy or not.
           */
          void QUAD_SPI_0_example(void)
          {
              struct _qspi_command cmd = {
                  .inst_frame.bits.inst_en = 1,
                  .inst_frame.bits.data_en = 1,
                  .inst_frame.bits.addr_en = 1,
                  .inst_frame.bits.dummy_cycles = 8,
                  .inst_frame.bits.tfr_type = QSPI_READMEM_ACCESS,
                  .instruction = 0x0B,
                  .address = 0,
                  .buf_len = 14,
                  .rx_buf = buf,
              };
              qspi_dma_register_callback(&QUAD_SPI_0, QSPI_DMA_CB_XFER_DONE,
                      xfer_complete_cb_QUAD_SPI_0);
              qspi_dma_enable(&QUAD_SPI_0);
              qspi_dma_serial_run_command(&QUAD_SPI_0, &cmd);
          }

Dependencies

QSPI peripheral and its related I/O lines and clocks
The NVIC must be configured so that QSPI interrupt requests are periodically serviced
DMA