This chapter documents the architecture and high-level design of ASF4. The ASF4 driver architecture (describes the ASF4 drivers) is built of three layers; HAL, HPL, and HRI. ASF4 has drivers which are designed to support Use-Cases, e.g. Timer and PWM drivers are use-cases of a Timer-Counter (TC) peripheral. Driver Variants are different driver implementation architectures, such the Synchronous-, Asynchronous-, DMA-, and RTOS-Drivers. Driver Types are; Peripheral-, Utility-, and Middleware-drivers.
The ASF4 project folder structure is described, followed by a walk-through of the system initialization sequence, which relies largely on Root Level Files in the project. The following sections describe in more detail elements within the project, namely Examples Folder, Pin Configuration, and a description of START configuration and the Config Folder.
More details are then given about the implementation of the three driver layers, respectively the Hardware Abstraction Layer (HAL), the Hardware Proxy Layer (HPL), and the Hardware Register Interface (HRI). For some of the drivers, there is an I/O system on top of the HAL interface, which disconnects middleware from any driver dependency because the middleware only needs to rely on the interface that the I/O system provides. Mechanisms for RTOS support are described. The implementations of various driver variants, such as Synchronous-, Asynchronous-, DMA-, and RTOS-Drivers, are described in the following chapter in Section Driver Implementation.