Contents

Description Features 3. Configuration Summary 4. Block Diagram 5. Signal Description 6. Microchip Recommended Power Management Solutions 6.1. MCP16502 PMIC 6.2. MCP16501 PMIC 7. Automotive Quality Grade 8. Safety and Security Features 8.1. Design for Safety and IEC60730 Class B Certification 8.1.1. Background Information 8.2. Design for Security 8.3. Safety and IEC 60730 Features 8.4. Security Features 9. Pinout 10. Power Considerations 10.1. Power Supplies 10.2. Power-up Considerations 10.3. Power-down Considerations 10.4. Power Supply Sequencing at Backup Mode Entry and Exit 10.4.1. VDDBU Power Architecture 10.4.2. Backup Mode Entry 10.4.3. Backup Mode Exit (Wake-up) 11. Memories 11.1. Embedded Memories 11.1.1. Internal SRAM 11.1.2. Internal ROM 11.1.3. Boot Strategies 11.2. External Memory 11.2.1. External Bus Interface 11.2.2. Supported Memories on DDR Interface 11.2.3. Supported Memories on Static Memories and NAND Flash Interfaces 11.2.4. DDR and SDMMC I/Os Calibration 11.2.4.1. DDR I/O Calibration 11.2.4.1.1. LPDDR2 Power Fail Management 11.2.4.2. SDMMC I/O Calibration 12. Event System 12.1. Real-time Event List 12.2. Real-time Event Mapping 13. System Controller 13.1. Power-On Reset 14. Peripherals 14.1. Peripheral Mapping 14.2. Peripheral Identifiers 14.3. Peripheral Signal Multiplexing on I/O Lines 14.4. Peripheral Clock Types 15. Chip Identifier (CHIPID) 15.1. Description 15.2. Embedded Characteristics 15.3. Register Summary 15.3.1. Chip ID Register 15.3.2. Chip ID Extension Register 16. Cortex-A5 Processor (ARM) 16.1. Reference Documents 16.2. Description 16.2.1. Power Management 16.2.1.1. Run Mode 16.2.1.2. Standby Mode 16.3. Embedded Characteristics 16.4. Block Diagram 16.5. Programmer Model 16.5.1. Processor Operating Modes 16.5.2. Processor Operating States 16.5.2.1. Switching State 16.5.3. Cortex-A5 Registers 16.5.3.1. CP15 Coprocessor 16.5.4. CP15 Register Access 16.5.5. Addresses in the Cortex-A5 Processor 16.5.6. Security Extensions Overview 16.5.6.1. System Boot Sequence 16.5.7. TrustZone 16.5.7.1. Hardware 16.5.7.2. Software 16.5.7.3. Debug 16.6. Memory Management Unit (MMU) 16.6.1. About the MMU 16.6.2. Memory Management System 16.6.2.1. Memory Types 16.6.3. Translation Lookaside Buffer (TLB) Organization 16.6.3.1. Micro TLB 16.6.3.2. Main TLB 16.6.4. Memory Access Sequence 16.6.5. Interaction with Memory System 16.6.6. External Aborts 16.6.6.1. External Aborts on Data Write 16.6.6.2. Synchronous and Asynchronous Aborts 16.6.7. MMU Software Accessible Registers 17. L2 Cache Controller (L2CC) 17.1. Description 17.2. Embedded Characteristics 17.3. Product Dependencies 17.3.1. Power Management 17.4. Functional Description 17.4.1. Double Linefill Issuing 17.5. Register Summary 17.5.1. L2CC Cache ID Register 17.5.2. L2CC Type Register 17.5.3. L2CC Control Register 17.5.4. L2CC Auxiliary Control Register 17.5.5. L2CC Tag RAM Latency Control Register 17.5.6. L2CC Data RAM Latency Control Register 17.5.7. L2CC Event Counter Control Register 17.5.8. L2CC Event Counter 1 Configuration Register 17.5.9. L2CC Event Counter 0 Configuration Register 17.5.10. L2CC Event Counter 1 Value Register 17.5.11. L2CC Event Counter 0 Value Register 17.5.12. L2CC Interrupt Mask Register 17.5.13. L2CC Masked Interrupt Status Register 17.5.14. L2CC Raw Interrupt Status Register 17.5.15. L2CC Interrupt Clear Register 17.5.16. L2CC Cache Synchronization Register 17.5.17. L2CC Invalidate Physical Address Line Register 17.5.18. L2CC Invalidate Way Register 17.5.19. L2CC Clean Physical Address Line Register 17.5.20. L2CC Clean Index Register 17.5.21. L2CC Clean Way Register 17.5.22. L2CC Clean Invalidate Physical Address Line Register 17.5.23. L2CC Clean Invalidate Index Register 17.5.24. L2CC Clean Invalidate Way Register 17.5.25. L2CC Data Lockdown Register 17.5.26. L2CC Instruction Lockdown Register 17.5.27. L2CC Debug Control Register 17.5.28. L2CC Prefetch Control Register 17.5.29. L2CC Power Control Register 18. Debug and Test Features 18.1. Description 18.2. Embedded Characteristics 18.3. Debug and Test Block Diagrams 18.4. Application Examples 18.4.1. Debug Environment 18.4.2. Test Environment 18.5. Debug and Test Pin Description 18.6. Functional Description 18.6.1. Test Pin 18.6.2. EmbeddedICE 18.6.3. JTAG Signal Description 18.6.4. IEEE 1149.1 JTAG Boundary Scan 18.7. Boundary JTAG ID Register 18.8. Cortex-A5 DP Identification Code Register IDCODE 18.8.1. JTAG Debug Port (JTAG-DP) 18.8.2. Serial Wire Debug Port (SW-DP) 19. Standard Boot Strategies 19.1. Description 19.2. Chip Access Using JTAG Connection 19.3. Flow Diagram 19.4. Chip Setup 19.5. Boot Configuration 19.5.1. Boot Configuration Word 19.5.2. Boot Sequence Controller Configuration Register 19.5.3. Backup Registers (BUREG) 19.5.4. Boot Configuration Word 19.5.5. NVM Boot Sequence 19.5.6. Valid Bootstrap Code Detection 19.5.6.1. Arm Exception Vectors Check 19.5.6.2. boot.bin File Check 19.5.7. Detailed Memory Boot Procedures 19.5.7.1. NAND Flash Boot: NAND Flash Detection 19.5.7.1.1. NAND Flash Specific Header Detection (Recommended Solution) 19.5.7.1.1.1. NAND Flash PMECC Register 19.5.7.1.1.2. ONFI 2.2 Parameters (Not Recommended) 19.5.7.2. NAND Flash Boot: PMECC Error Detection and Correction 19.5.7.3. SDCard/e.MMC Boot 19.5.7.4. SPI Flash Boot 19.5.7.4.1. Supported DataFlash Devices 19.5.7.4.2. Supported Serial Flash Devices 19.5.7.5. QSPI NOR Flash Boot 19.5.7.5.1. Supported QSPI Memories by Manufacturer 19.5.7.5.2. Hardware Considerations 19.5.7.5.3. Software Considerations 19.5.7.5.3.1. QSPI NOR memories with SFDP (JEDEC JESD216x compliant) 19.5.7.5.3.2. QSPI NOR memories without SFDP 19.5.8. Hardware and Software Constraints 19.6. SAM-BA Monitor 19.6.1. Command List 19.6.2. UART Port 19.6.3. Xmodem Protocol 19.6.4. USB Device Port 19.6.4.1. Supported External Crystal/External Clocks 19.6.4.2. USB Class 19.6.4.3. Enumeration Process 19.6.4.4. Communication Endpoints 19.7. Fuse Box Controller 19.7.1. Fuse Bit Mapping 20. CPU System Bus Matrix (CPUMX) 20.1. Description 20.2. Embedded Characteristics 20.3. Block Diagram 20.4. Operation 20.4.1. Remap 20.5. Register Summary 20.5.1. CPU System Bus Matrix Remap Register 21. Matrix (H64MX/H32MX) 21.1. Description 21.2. Embedded Characteristics 21.3. 64-bit Matrix (H64MX) 21.3.1. Matrix Hosts 21.3.2. Matrix Clients 21.3.3. Host to Client Access 21.4. 32-bit Matrix (H32MX) 21.4.1. Matrix Hosts 21.4.2. Matrix Clients 21.4.3. Host to Client Access 21.5. Memory Mapping 21.6. Special Bus Granting Mechanism 21.7. No Default Host 21.8. Last Access Host 21.9. Fixed Default Host 21.10. Arbitration 21.10.1. Arbitration Scheduling 21.10.1.1. Undefined Length Burst Arbitration 21.10.1.2. Slot Cycle Limit Arbitration 21.10.2. Arbitration Priority Scheme 21.10.2.1. Fixed Priority Arbitration 21.10.2.2. Round-Robin Arbitration 21.11. Register Write Protection 21.12. TrustZone Technology 21.12.1. Security Types of Clients 21.12.1.1. Principles 21.12.1.2. Examples 21.12.2. Security Types of SDMMC System Bus Clients 21.12.3. Security Types of System Bus Hosts 21.12.4. Security of Peripheral Bus Clients 21.13. Register Summary 21.13.1. Bus Matrix Host Configuration Registers 21.13.2. Bus Matrix Client Configuration Registers 21.13.3. Bus Matrix Priority Registers A For Clients 21.13.4. Bus Matrix Priority Registers B For Clients 21.13.5. Host Error Interrupt Enable Register 21.13.6. Host Error Interrupt Disable Register 21.13.7. Host Error Interrupt Mask Register 21.13.8. Host Error Status Register 21.13.9. Host Error Address Registers 21.13.10. Write Protection Mode Register 21.13.11. Write Protection Status Register 21.13.12. Security Client Register 21.13.13. Security Areas Split Client Registers 21.13.14. Security Region Top Client Registers 21.13.15. Security Peripheral Select x Registers 22. Special Function Registers (SFR) 22.1. Description 22.2. Embedded Characteristics 22.3. Register Summary 22.3.1. DDR Configuration Register 22.3.2. OHCI Interrupt Configuration Register 22.3.3. OHCI Interrupt Status Register 22.3.4. Security Configuration Register 22.3.5. UTMI Clock Trimming Register 22.3.6. UTMI High-Speed Trimming Register 22.3.7. UTMI Full-Speed Trimming Register 22.3.8. UMTI DP/DM Pin Swapping Register 22.3.9. CAN Memories Address-based Register 22.3.10. Serial Number 0 Register 22.3.11. Serial Number 1 Register 22.3.12. AIC Interrupt Redirection Register 22.3.13. HRAMC L2CC Register 22.3.14. I2S Register 22.3.15. QSPI Clock Pad Supply Select Register 23. Special Function Registers Backup (SFRBU) 23.1. Description 23.2. Embedded Characteristics 23.3. Register Summary 23.3.1. SFRBU Power Switch BU Control Register 23.3.2. SFRBU DDR BU Mode Control Register 23.3.3. SFRBU RXLP Pull-Up Control Register 24. Advanced Interrupt Controller (AIC) 24.1. Description 24.2. Embedded Characteristics 24.3. Block Diagram 24.4. Application Block Diagram 24.5. Detailed Block Diagram 24.6. I/O Line Description 24.7. Product Dependencies 24.7.1. I/O Lines 24.7.2. Power Management 24.7.3. Interrupt Sources 24.8. Functional Description 24.8.1. Interrupt Source Control 24.8.1.1. Interrupt Source Mode 24.8.1.2. Interrupt Source Enabling 24.8.1.3. Interrupt Clearing and Setting 24.8.1.4. Interrupt Status 24.8.1.5. Internal Interrupt Source Input Stage 24.8.1.6. External Interrupt Source Input Stage 24.8.2. Interrupt Latencies 24.8.2.1. External Interrupt Edge Triggered Source 24.8.2.2. External Interrupt Level Sensitive Source 24.8.2.3. Internal Interrupt Edge Triggered Source 24.8.2.4. Internal Interrupt Level Sensitive Source 24.8.3. Normal Interrupt 24.8.3.1. Priority Controller 24.8.3.2. Interrupt Nesting 24.8.3.3. Interrupt Handlers 24.8.4. Fast Interrupt 24.8.4.1. Fast Interrupt Source 24.8.4.2. Fast Interrupt Control 24.8.4.3. Fast Interrupt Handlers 24.8.5. Protect Mode 24.8.6. Spurious Interrupt 24.8.7. General Interrupt Mask 24.8.8. Register Write Protection 24.9. Register Summary 24.9.1. AIC Source Select Register 24.9.2. AIC Source Mode Register 24.9.3. AIC Source Vector Register 24.9.4. AIC Interrupt Vector Register 24.9.5. AIC FIQ Vector Register 24.9.6. AIC Interrupt Status Register 24.9.7. AIC Interrupt Pending Register 0 24.9.8. AIC Interrupt Pending Register 1 24.9.9. AIC Interrupt Pending Register 2 24.9.10. AIC Interrupt Pending Register 3 24.9.11. AIC Interrupt Mask Register 24.9.12. AIC Core Interrupt Status Register 24.9.13. AIC End of Interrupt Command Register 24.9.14. AIC Spurious Interrupt Vector Register 24.9.15. AIC Interrupt Enable Command Register 24.9.16. AIC Interrupt Disable Command Register 24.9.17. AIC Interrupt Clear Command Register 24.9.18. AIC Interrupt Set Command Register 24.9.19. AIC Debug Control Register 24.9.20. AIC Write Protection Mode Register 24.9.21. AIC Write Protection Status Register 25. Watchdog Timer (WDT) 25.1. Description 25.2. Embedded Characteristics 25.3. Block Diagram 25.4. Functional Description 25.5. Register Summary 25.5.1. Watchdog Timer Control Register 25.5.2. Watchdog Timer Mode Register 25.5.3. Watchdog Timer Status Register 26. Reset Controller (RSTC) 26.1. Description 26.2. Embedded Characteristics 26.3. Block Diagram 26.4. Functional Description 26.4.1. Reset Controller Overview 26.4.2. NRST Manager 26.4.2.1. NRST Signal or Interrupt 26.4.3. Reset States 26.4.3.1. General Reset 26.4.3.2. Wake-up Reset 26.4.3.3. User Reset 26.4.3.4. Software Reset 26.4.3.5. Watchdog Reset 26.4.3.6. 32.768 kHz Crystal Oscillator Failure Detection Reset 26.4.4. Reset State Priorities 26.5. Register Summary 26.5.1. Reset Controller Control Register 26.5.2. Reset Controller Status Register 26.5.3. Reset Controller Mode Register 27. Shutdown Controller (SHDWC) 27.1. Description 27.2. Embedded Characteristics 27.3. Block Diagram 27.4. I/O Lines Description 27.5. Product Dependencies 27.5.1. Power Management 27.6. Functional Description 27.6.1. Wake-up Inputs 27.7. Register Summary 27.7.1. SHDWC Control Register 27.7.2. SHDWC Mode Register 27.7.3. SHDWC Status Register 27.7.4. SHDWC Wake-up Inputs Register 28. Periodic Interval Timer (PIT) 28.1. Description 28.2. Embedded Characteristics 28.3. Block Diagram 28.4. Functional Description 28.5. Register Summary 28.5.1. Periodic Interval Timer Mode Register 28.5.2. Periodic Interval Timer Status Register 28.5.3. Periodic Interval Timer Value Register 28.5.4. Periodic Interval Timer Image Register 29. Real-time Clock (RTC) 29.1. Description 29.2. Embedded Characteristics 29.3. Block Diagram 29.4. Product Dependencies 29.4.1. Power Management 29.4.2. Interrupt 29.5. Functional Description 29.5.1. Reference Clock 29.5.2. Timing 29.5.3. Alarm 29.5.4. Error Checking when Programming 29.5.5. RTC Internal Free-Running Counter Error Checking 29.5.6. Updating Time/Calendar 29.5.6.1. Gregorian and Persian Modes 29.5.6.2. UTC Mode 29.5.7. RTC Accurate Clock Calibration 29.5.8. Waveform Generation 29.5.9. Tamper Timestamping 29.6. Register Summary 29.6.1. RTC Control Register 29.6.2. RTC Mode Register 29.6.3. RTC Time Register 29.6.4. RTC Time Register (UTC_MODE) 29.6.5. RTC Calendar Register 29.6.6. RTC Time Alarm Register 29.6.7. RTC Time Alarm Register (UTC_MODE) 29.6.8. RTC Calendar Alarm Register 29.6.9. RTC Calendar Alarm Register (UTC_MODE) 29.6.10. RTC Status Register 29.6.11. RTC Status Clear Command Register 29.6.12. RTC Interrupt Enable Register 29.6.13. RTC Interrupt Disable Register 29.6.14. RTC Interrupt Mask Register 29.6.15. RTC Valid Entry Register 29.6.16. RTC TimeStamp Time Register 0 29.6.17. RTC TimeStamp Time Register 0 (UTC_MODE) 29.6.18. RTC TimeStamp Time Register 1 29.6.19. RTC TimeStamp Time Register 1 (UTC_MODE) 29.6.20. RTC TimeStamp Date Register 29.6.21. RTC TimeStamp Date Register (UTC_MODE) 29.6.22. RTC TimeStamp Source Register 30. System Controller Write Protection (SYSCWP) 30.1. Functional Description 30.1.1. System Controller Peripheral Mapping 30.1.2. Register Write Protection 30.2. Register Summary 30.2.1. SYSC Write Protection Mode Register 31. Slow Clock Controller (SCKC) 31.1. Description 31.2. Embedded Characteristics 31.3. Block Diagram 31.4. Functional Description 31.4.1. Switching from Embedded Always-on 64 kHz RC Oscillator to 32.768 kHz Crystal Oscillator 31.4.2. Switching from 32.768 kHz Crystal Oscillator to Embedded Always-on 64 kHz RC Oscillator 31.5. Register Summary 31.5.1. Slow Clock Controller Configuration Register 32. Peripheral Touch Controller (PTC) 32.1. Description 32.2. Embedded Characteristics 32.3. Block Diagram 32.4. Signal Description 32.5. Product Dependencies 32.5.1. Power Management 32.5.2. I/O Lines 32.5.3. Interrupt Sources 32.6. Functional Description 32.6.1. picoPower Processor (pPP) 32.6.2. Shared Memories 32.6.2.1. Mailbox 32.6.2.2. SRAM Data Area 32.6.2.3. Firmware in SRAM Code Area 32.6.2.4. Host Interface 32.6.2.4.1. Processor Command Registers 32.6.3. PTC Digital Controller 32.6.3.1. PTC Digital Controller Operations 32.6.4. PTC Analog Front End (AFE) 32.6.5. Operations in Mutual Capacitance 32.6.6. Operations in Self-capacitance 32.7. Register Summary 32.7.1. PTC Command Register 32.7.2. PTC Interrupt Status Register 32.7.3. PTC Enable Register 33. Low Power Asynchronous Receiver (RXLP) 33.1. Description 33.2. Embedded Characteristics 33.3. Block Diagram 33.4. Product Dependencies 33.4.1. Power Management 33.5. Functional Description 33.5.1. Baud Rate Generator 33.5.2. Receiver 33.5.2.1. Receiver Reset, Enable and Disable 33.5.2.2. Start Detection and Data Sampling 33.5.2.3. Parity Error 33.5.2.4. Receiver Framing Error 33.5.2.5. Receiver Digital Filter 33.5.3. Comparison Function on Received Character 33.5.4. Register Write Protection 33.6. Register Summary 33.6.1. RXLP Control Register 33.6.2. RXLP Mode Register 33.6.3. RXLP Receiver Holding Register 33.6.4. RXLP Baud Rate Generator Register 33.6.5. RXLP Comparison Register 33.6.6. RXLP Write Protection Mode Register 34. Clock Generator 34.1. Description 34.2. Embedded Characteristics 34.3. Block Diagram 34.4. Slow Clock 34.4.1. Embedded 64 kHz (typical) RC Oscillator 34.4.2. 32.768 kHz Crystal Oscillator 34.5. Main Clock 34.5.1. 12 MHz RC Oscillator 34.5.2. 8 to 24 MHz Crystal Oscillator 34.5.3. Main Clock Source Selection 34.5.4. Bypassing the 8 to 24 MHz Crystal Oscillator 34.5.5. Main Frequency Counter 34.5.6. Switching Main Clock Between the RC Oscillator and the Crystal Oscillator 34.6. Divider and PLLA Block 34.6.1. Divider and Phase Lock Loop Programming 34.7. UTMI PLL Clock 34.8. Audio PLL 35. Power Management Controller (PMC) 35.1. Description 35.2. Embedded Characteristics 35.3. Block Diagram 35.4. Main System Bus Clock Controller 35.5. Processor Clock Controller 35.6. Matrix Clock Controller 35.7. Programmable Clock Controller 35.8. Core and Bus Independent Clocks for Peripherals 35.9. Peripheral and Generic Clock Controller 35.10. LCDC Clock Controller 35.11. ISC Clock Controller 35.12. USB Device and Host Clocks 35.13. DDR2/LPDDR/LPDDR2 Clock Controller 35.14. Fast Start-up from Ultra-Low-Power 0 (ULP0) Mode 35.15. Fast Start-up from Ultra-Low-Power 1 (ULP1) Mode 35.16. Asynchronous Partial Wake-up 35.16.1. Description 35.16.2. System Asynchronous Partial Wake-Up 35.16.2.1. Configuration Procedure 35.16.3. Asynchronous Partial Wake-Up of a Peripheral in Active Mode 35.16.3.1. Configuration Procedure 35.17. Main Crystal Oscillator Failure Detection 35.18. 32.768 kHz Crystal Oscillator Frequency Monitor 35.19. Programming Sequence 35.20. Clock Switching Details 35.20.1. Main System Bus Clock Switching Timings 35.20.2. Clock Switching Waveforms 35.21. Register Write Protection 35.22. Register Summary 35.22.1. PMC System Clock Enable Register 35.22.2. PMC System Clock Disable Register 35.22.3. PMC System Clock Status Register 35.22.4. PMC Peripheral Clock Enable Register 0 35.22.5. PMC Peripheral Clock Disable Register 0 35.22.6. PMC Peripheral Clock Status Register 0 35.22.7. PMC UTMI Clock Configuration Register 35.22.8. PMC Clock Generator Main Oscillator Register 35.22.9. PMC Clock Generator Main Clock Frequency Register 35.22.10. PMC Clock Generator PLLA Register 35.22.11. PMC Main System Bus Clock Register 35.22.12. PMC USB Clock Register 35.22.13. PMC_PCKx 35.22.14. PMC Interrupt Enable Register 35.22.15. PMC Interrupt Disable Register 35.22.16. PMC Status Register 35.22.17. PMC Interrupt Mask Register 35.22.18. PMC Fast Startup Polarity Register 35.22.19. PMC Fast Start-up Mode Register 35.22.20. PMC Fault Output Clear Register 35.22.21. PLL Charge Pump Current Register 35.22.22. PMC Write Protection Mode Register 35.22.23. PMC Write Protection Status Register 35.22.24. PMC Peripheral Clock Enable Register 1 35.22.25. PMC Peripheral Clock Disable Register 1 35.22.26. PMC Peripheral Clock Status Register 1 35.22.27. PMC Peripheral Control Register 35.22.28. PMC Asynchronous Partial Wake-Up Enable Register 0 35.22.29. PMC Asynchronous Partial Wake-Up Disable Register 0 35.22.30. PMC Asynchronous Partial Wake-Up Status Register 0 35.22.31. PMC Asynchronous Partial Wake-Up Activity Status Register 0 35.22.32. PMC Asynchronous Partial Wake-Up Enable Register 1 35.22.33. PMC Asynchronous Partial Wake-Up Disable Register 1 35.22.34. PMC Asynchronous Partial Wake-Up Status Register 1 35.22.35. PMC Asynchronous Partial Wake-Up Activity Status Register 1 35.22.36. PMC Asynchronous Partial Wake-Up Activity In Progress Register 35.22.37. PMC Asynchronous Partial Wake-Up Control Register 35.22.38. PMC Audio PLL Control Register 0 35.22.39. PMC Audio PLL Control Register 1 36. Parallel Input/Output Controller (PIO) 36.1. Description 36.2. Embedded Characteristics 36.3. Block Diagram 36.4. Product Dependencies 36.4.1. Pin Multiplexing 36.4.2. External Interrupt Lines 36.4.3. Power Management 36.4.4. Interrupt Generation 36.5. Functional Description 36.5.1. I/O Line Configuration Method 36.5.1.1. Security Management 36.5.1.2. Programming I/O Line Configuration 36.5.1.3. Reading the I/O Line Configuration 36.5.2. Pull-Up and Pull-Down Resistor Control 36.5.3. General Purpose or Peripheral Function Selection 36.5.4. Output Control 36.5.5. Synchronous Data Output 36.5.6. Open-Drain Mode 36.5.7. Output Line Timings 36.5.8. Inputs 36.5.9. Input Glitch and Debouncing Filters 36.5.10. Input Edge/Level Interrupt 36.5.11. Interrupt Management 36.5.12. I/O Lines Lock 36.5.13. Programmable I/O Drive 36.5.14. Programmable Schmitt Trigger 36.5.15. I/O Line Configuration Freeze 36.5.15.1. Introduction 36.5.15.2. Software Freeze 36.5.15.2.1. Physical Freeze 36.5.15.2.2. Interrupt Freeze 36.5.16. Register Write Protection 36.6. I/O Lines Programming Example 36.7. Register Summary 36.7.1. PIO Mask Register 36.7.2. PIO Configuration Register 36.7.3. PIO Pin Data Status Register 36.7.4. PIO Lock Status Register 36.7.5. PIO Set Output Data Register 36.7.6. PIO Clear Output Data Register 36.7.7. PIO Output Data Status Register 36.7.8. PIO Interrupt Enable Register 36.7.9. PIO Interrupt Disable Register 36.7.10. PIO Interrupt Mask Register 36.7.11. PIO Interrupt Status Register 36.7.12. PIO I/O Freeze Configuration Register 36.7.13. PIO Write Protection Mode Register 36.7.14. PIO Write Protection Status Register 36.7.15. Secure PIO Mask Register 36.7.16. Secure PIO Configuration Register 36.7.17. Secure PIO Pin Data Status Register 36.7.18. Secure PIO Lock Status Register 36.7.19. Secure PIO Set Output Data Register 36.7.20. Secure PIO Clear Output Data Register 36.7.21. Secure PIO Output Data Status Register 36.7.22. Secure PIO Interrupt Enable Register 36.7.23. Secure PIO Interrupt Disable Register 36.7.24. Secure PIO Interrupt Mask Register 36.7.25. Secure PIO Interrupt Status Register 36.7.26. Secure PIO Set I/O Non-Secure Register 36.7.27. Secure PIO Set I/O Secure Register 36.7.28. Secure PIO I/O Security Status Register 36.7.29. Secure PIO I/O Freeze Configuration Register 36.7.30. Secure PIO Slow Clock Divider Debouncing Register 36.7.31. Secure PIO Write Protection Mode Register 36.7.32. Secure PIO Write Protection Status Register 37. External Memories 37.1. Multiport DDR-SDRAM Controller (MPDDRC) 37.1.1. Description 37.1.2. MPDDR Controller Block Diagram 37.1.3. IO Lines Description 37.1.4. Product Dependencies 37.1.5. Implementation Examples 37.1.5.1. 16-bit DDR2 37.1.5.2. 2x16-bit DDR2 37.1.5.3. 16-bit DDR3/DDR3L 37.1.5.4. 2x16-bit DDR3/DDR3L 37.1.5.5. 2x16-bit LPDDR2/LPDDR3 37.2. External Bus Interface (EBI) 37.2.1. Description 37.2.2. Implementation Examples 37.2.2.1. 8-bit NAND Flash 37.2.2.2. 16-bit NAND Flash 37.2.2.3. NOR Flash on NCS0 38. DDR-SDRAM Controller (MPDDRC) 38.1. Description 38.2. Embedded Characteristics 38.3. Block Diagram 38.4. Product Dependencies, Initialization Sequence 38.4.1. Low-power DDR1-SDRAM Initialization 38.4.2. DDR2-SDRAM Initialization 38.4.3. Low-power DDR2-SDRAM Initialization 38.4.4. DDR3-SDRAM/DDR3L-SDRAM Initialization 38.4.5. Low-power DDR3-SDRAM Initialization 38.5. Functional Description 38.5.1. DDR-SDRAM Controller Write Cycle 38.5.2. DDR-SDRAM Controller Read Cycle 38.5.3. Refresh (Auto-Refresh Command) 38.5.3.1. All Banks Auto-Refresh 38.5.3.2. Per-Bank Auto-Refresh 38.5.3.3. Adjust Auto-Refresh Rate 38.5.4. Power Management 38.5.4.1. Self-Refresh Mode 38.5.4.2. Power-Down Mode 38.5.4.3. Deep Power-Down Mode 38.5.4.4. Change Frequency During Self-Refresh Mode with Low-power DDR-SDRAM and DDR3-SDRAM Devices 38.5.4.5. Reset Mode 38.5.5. Optimized Access Functionality 38.5.5.1. Round-robin Arbitration 38.5.5.2. Request-word Weighted Round-robin Arbitration 38.5.5.3. Bandwidth Weighted Round-robin Arbitration 38.5.6. Scrambling/Unscrambling Function 38.5.7. Register Write Protection 38.5.8. Monitor 38.6. Software Interface/SDRAM Organization, Address Mapping 38.6.1. DDR-SDRAM Address Mapping for 16-bit Memory Data Bus Width 38.6.2. DDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width 38.6.3. DDR-SDRAM Address Mapping for Low-cost Memories 38.7. Register Summary 38.7.1. MPDDRC Mode Register 38.7.2. MPDDRC Refresh Timer Register 38.7.3. MPDDRC Configuration Register 38.7.4. MPDDRC Timing Parameter 0 Register 38.7.5. MPDDRC Timing Parameter 1 Register 38.7.6. MPDDRC Timing Parameter 2 Register 38.7.7. MPDDRC Low-Power Register 38.7.8. MPDDRC Memory Device Register 38.7.9. MPDDRC Low-power DDR2 Low-power DDR3 Low-power Register 38.7.10. MPDDRC Low-power DDR2 Low-power DDR3 and DDR3 Calibration and MR4 Register 38.7.11. MPDDRC Low-power DDR2 Low-power DDR3 and DDR3 Timing Calibration Register 38.7.12. MPDDRC I/O Calibration Register 38.7.13. MPDDRC OCMS Register 38.7.14. MPDDRC OCMS KEY1 Register 38.7.15. MPDDRC OCMS KEY2 Register 38.7.16. MPDDRC Configuration Arbiter Register 38.7.17. MPDDRC Timeout Register 38.7.18. MPDDRC Request Port 0-1-2-3 Register 38.7.19. MPDDRC Request Port 4-5-6-7 Register 38.7.20. MPDDRC Current/Maximum Bandwidth Port 0-1-2-3 Register 38.7.21. MPDDRC Current/Maximum Bandwidth Port 4-5-6-7 Register 38.7.22. MPDDRC Read Data Path Register 38.7.23. MPDDRC Monitor Configuration Register 38.7.24. MPDDRC Monitor Address High/Low Port x Register 38.7.25. MPDDRC_MINFOx (MAX_WAIT) 38.7.26. MPDDRC_MINFOx (NB_TRANSFERS) 38.7.27. MPDDRC_MINFOx (TOTAL_LATENCY) 38.7.28. MPDDRC Write Protection Mode Register 38.7.29. MPDDRC Write Protection Status Register 39. Static Memory Controller (SMC) 39.1. Description 39.2. Embedded Characteristics 39.3. Block Diagram 39.4. I/O Lines Description 39.5. Multiplexed Signals 39.6. Application Example 39.6.1. Hardware Interface 39.7. Product Dependencies 39.7.1. I/O Lines 39.7.2. Power Management 39.7.3. Interrupt Sources 39.8. External Memory Mapping 39.9. Connection to External Devices 39.9.1. Data Bus Width 39.9.2. Byte Write or Byte Select Access 39.9.2.1. Byte Write Access 39.9.2.2. Byte Select Access 39.9.2.3. Signal Multiplexing 39.10. Standard Read and Write Protocols 39.10.1. Read Waveforms 39.10.1.1. NRD Waveform 39.10.1.2. NCS Waveform 39.10.1.3. Read Cycle 39.10.2. Read Mode 39.10.2.1. Read is Controlled by NRD (READ_MODE = 1) 39.10.2.2. Read is Controlled by NCS (READ_MODE = 0) 39.10.3. Write Waveforms 39.10.3.1. NWE Waveforms 39.10.3.2. NCS Waveforms 39.10.3.3. Write Cycle 39.10.4. Write Mode 39.10.4.1. Write is Controlled by NWE (WRITE_MODE = 1) 39.10.4.2. Write is Controlled by NCS (WRITE_MODE = 0) 39.10.5. Coding Timing Parameters 39.10.6. Reset Values of Timing Parameters 39.10.7. Usage Restriction 39.10.7.1. For Read Operations 39.10.7.2. For Write Operations 39.10.7.3. For Read and Write Operations 39.11. Scrambling/Unscrambling Function 39.12. Automatic Wait States 39.12.1. Chip Select Wait States 39.12.2. Early Read Wait State 39.12.3. Reload User Configuration Wait State 39.12.3.1. User Procedure 39.12.3.2. Slow Clock Mode Transition 39.12.4. Read to Write Wait State 39.13. Data Float Wait States 39.13.1. READ_MODE 39.13.2. TDF Optimization Enabled (TDF_MODE = 1) 39.13.3. TDF Optimization Disabled (TDF_MODE = 0) 39.14. External Wait 39.14.1. Restriction 39.14.2. Frozen Mode 39.14.3. Ready Mode 39.14.4. NWAIT Latency and Read/Write Timings 39.15. Slow Clock Mode 39.15.1. Slow Clock Mode Waveforms 39.15.2. Switching from (to) Slow Clock Mode to (from) Normal Mode 39.16. Register Write Protection 39.17. NFC Operations 39.17.1. NFC Overview 39.17.2. NFC Control Registers 39.17.2.1. Building NFC Address Command Example 39.17.2.2. NFCADDR_CMD 39.17.2.3. NFCDATA_ADDT 39.17.2.4. NFCDATA_STATUS 39.17.3. NFC Initialization 39.17.3.1. NFC Timing Engine 39.17.4. NFC SRAM 39.17.4.1. NFC SRAM Mapping 39.17.4.2. NFC SRAM Access Prioritization Algorithm 39.17.5. NAND Flash Operations 39.17.5.1. Page Read 39.17.5.2. Program Page 39.18. PMECC Controller Functional Description 39.18.1. MLC/SLC Write Page Operation Using PMECC 39.18.1.1. SLC/MLC Write Operation with Spare Enable Bit Set 39.18.1.2. SLC/MLC Write Operation with Spare Disable 39.18.2. MLC/SLC Read Page Operation Using PMECC 39.18.2.1. MLC/SLC Read Operation with Spare Decoding 39.18.2.2. MLC/SLC Read Operation 39.18.2.3. MLC/SLC User Read ECC Area 39.18.2.4. MLC Controller Working with NFC 39.19. Software Implementation 39.19.1. Remainder Substitution Procedure 39.19.2. Finding the Error Location Polynomial Sigma(x) 39.19.3. Finding the Error Position 39.19.3.1. Error Location 39.20. Register Summary 39.20.1. NFC Configuration Register 39.20.2. NFC Control Register 39.20.3. HSMC_SR 39.20.4. NFC Interrupt Enable Register 39.20.5. NFC Interrupt Disable Register 39.20.6. NFC Interrupt Mask Register 39.20.7. NFC Address Cycle Zero Register 39.20.8. NFC Bank Register 39.20.9. PMECC Configuration Register 39.20.10. PMECC Spare Area Size Register 39.20.11. PMECC Start Address Register 39.20.12. PMECC End Address Register 39.20.13. PMECC Control Register 39.20.14. PMECC Status Register 39.20.15. PMECC Interrupt Enable Register 39.20.16. PMECC Interrupt Disable Register 39.20.17. PMECC Interrupt Mask Register 39.20.18. PMECC Interrupt Status Register 39.20.19. PMECC Redundancy x Register 39.20.20. PMECC Remainder x Register 39.20.21. PMECC Error Location Configuration Register 39.20.22. PMECC Error Location Primitive Register 39.20.23. PMECC Error Location Enable Register 39.20.24. PMECC Error Location Disable Register 39.20.25. PMECC Error Location Status Register 39.20.26. PMECC Error Location Interrupt Enable Register 39.20.27. PMECC Error Location Interrupt Disable Register 39.20.28. PMECC Error Location Interrupt Mask Register 39.20.29. PMECC Error Location Interrupt Status Register 39.20.30. PMECC Error Location SIGMA0 Register 39.20.31. PMECC Error Location SIGMAx Register 39.20.32. PMECC Error Location x Register 39.20.33. Setup Register 39.20.34. Pulse Register 39.20.35. Cycle Register 39.20.36. Timings Register 39.20.37. Mode Register 39.20.38. Off Chip Memory Scrambling Register 39.20.39. Off Chip Memory Scrambling Key1 Register 39.20.40. Off Chip Memory Scrambling Key2 Register 39.20.41. Write Protection Mode Register 39.20.42. Write Protection Status Register 40. DMA Controller (XDMAC) 40.1. Description 40.2. Embedded Characteristics 40.3. Block Diagram 40.4. DMA Controller Peripheral Connections 40.5. Functional Description 40.5.1. Basic Definitions 40.5.2. Data Striding Diagram 40.5.3. Transfer Hierarchy Diagrams 40.5.4. Peripheral Synchronized Transfer 40.5.4.1. Peripheral to Memory Transfer 40.5.4.2. Memory to Peripheral Transfer 40.5.4.3. Software Triggered Synchronized Transfer 40.5.5. XDMAC Transfer Software Operation 40.5.5.1. Single Block Transfer With Single Microblock 40.5.5.2. Single Block Transfer With Multiple Microblock 40.5.5.3. Host Transfer 40.5.5.4. Disabling A Channel Before Transfer Completion 40.6. Linked List Descriptor Operation 40.6.1. Linked List Descriptor View 40.6.1.1. Channel Next Descriptor View 0–3 Structures 40.6.2. Descriptor Structure Members Description 40.6.2.1. MBR_UBC 40.7. XDMAC Maintenance Software Operations 40.7.1. Disabling a Channel 40.7.2. Suspending a Channel 40.7.3. Flushing a Channel 40.7.4. Maintenance Operation Priority 40.7.4.1. Disable Operation Priority 40.7.4.2. Flush Operation Priority 40.7.4.3. Suspend Operation Priority 40.8. XDMAC Software Requirements 40.9. Register Summary 40.9.1. XDMAC_GTYPE 40.9.2. XDMAC Global Configuration Register 40.9.3. XDMAC Global Weighted Arbiter Configuration Register 40.9.4. XDMAC Global Interrupt Enable Register 40.9.5. XDMAC Global Interrupt Disable Register 40.9.6. XDMAC Global Interrupt Mask Register 40.9.7. XDMAC Global Interrupt Status Register 40.9.8. XDMAC Global Channel Enable Register 40.9.9. XDMAC Global Channel Disable Register 40.9.10. XDMAC Global Channel Status Register 40.9.11. XDMAC Global Channel Read Suspend Register 40.9.12. XDMAC Global Channel Write Suspend Register 40.9.13. XDMAC Global Channel Read Write Suspend Register 40.9.14. XDMAC Global Channel Read Write Resume Register 40.9.15. XDMAC Global Channel Software Request Register 40.9.16. XDMAC Global Channel Software Request Status Register 40.9.17. XDMAC Global Channel Software Flush Request Register 40.9.18. XDMAC Channel x Interrupt Enable Register [x=0..15] 40.9.19. XDMAC Channel x Interrupt Disable Register [x = 0..15] 40.9.20. XDMAC Channel x Interrupt Mask Register [x = 0..15] 40.9.21. XDMAC Channel x Interrupt Status Register [x = 0..15] 40.9.22. XDMAC Channel x Source Address Register [x = 0..15] 40.9.23. XDMAC Channel x Destination Address Register [x = 0..15] 40.9.24. XDMAC Channel x Next Descriptor Address Register [x = 0..15] 40.9.25. XDMAC Channel x Next Descriptor Control Register [x = 0..15] 40.9.26. XDMAC Channel x Microblock Control Register [x = 0..15] 40.9.27. XDMAC Channel x Block Control Register [x = 0..15] 40.9.28. XDMAC Channel x Configuration Register [x = 0..15] 40.9.29. XDMAC Channel x Data Stride Memory Set Pattern Register [x = 0..15] 40.9.30. XDMAC Channel x Source Microblock Stride Register [x = 0..15] 40.9.31. XDMAC Channel x Destination Microblock Stride Register [x = 0..15] 41. LCD Controller (LCDC) 41.1. Description 41.2. Embedded Characteristics 41.3. Block Diagram 41.4. I/O Lines Description 41.5. Product Dependencies 41.5.1. I/O Lines 41.5.2. Power Management 41.5.3. Interrupt Sources 41.6. Functional Description 41.6.1. Timing Engine Configuration 41.6.1.1. Pixel Clock Period Configuration 41.6.1.2. Horizontal and Vertical Synchronization Configuration 41.6.1.3. Timing Engine Powerup Software Operation 41.6.1.4. Timing Engine Powerdown Software Operation 41.6.2. DMA Software Operations 41.6.2.1. DMA Channel Descriptor (DSCR) Alignment and Structure 41.6.2.2. Enabling a DMA Channel 41.6.2.3. Disabling a DMA Channel 41.6.2.4. DMA Dynamic Linking of a New Transfer Descriptor 41.6.2.5. DMA Interrupt Generation 41.6.2.6. DMA Address Alignment Requirements 41.6.3. Overlay Software Configuration 41.6.3.1. System Bus Access Attributes 41.6.3.2. Color Attributes 41.6.3.3. Window Position, Size, Scaling and Striding Attributes 41.6.3.4. Overlay Blender Attributes 41.6.3.5. Overlay Attributes Software Operation 41.6.4. RGB Frame Buffer Memory Bitmap 41.6.4.1. 1 bpp Through Color Lookup Table 41.6.4.2. 2 bpp Through Color Lookup Table 41.6.4.3. 4 bpp Through Color Lookup Table 41.6.4.4. 8 bpp Through Color Lookup Table 41.6.4.5. 12 bpp Memory Mapping, RGB 4:4:4 41.6.4.6. 16 bpp Memory Mapping with Alpha Channel, ARGB 4:4:4:4 41.6.4.7. 16 bpp Memory Mapping with Alpha Channel, RGBA 4:4:4:4 41.6.4.8. 16 bpp Memory Mapping with Alpha Channel, RGB 5:6:5 41.6.4.9. 16 bpp Memory Mapping with Transparency Bit, ARGB 1:5:5:5 41.6.4.10. 18 bpp Unpacked Memory Mapping with Transparency Bit, RGB 6:6:6 41.6.4.11. 18 bpp Packed Memory Mapping with Transparency Bit, RGB 6:6:6 41.6.4.12. 19 bpp Unpacked Memory Mapping with Transparency Bit, RGB 1:6:6:6 41.6.4.13. 19 bpp Packed Memory Mapping with Transparency Bit, ARGB 1:6:6:6 41.6.4.14. 24 bpp Unpacked Memory Mapping, RGB 8:8:8 41.6.4.15. 24 bpp Packed Memory Mapping, RGB 8:8:8 41.6.4.16. 25 bpp Memory Mapping, ARGB 1:8:8:8 41.6.4.17. 32 bpp Memory Mapping, ARGB 8:8:8:8 41.6.4.18. 32 bpp Memory Mapping, RGBA 8:8:8:8 41.6.5. YUV Frame Buffer Memory Mapping 41.6.5.1. AYCbCr 4:4:4 Packed Frame Buffer Memory Mapping 41.6.5.2. 4:2:2 Packed Mode Frame Buffer Memory Mapping 41.6.5.3. 4:2:2 Semiplanar Mode Frame Buffer Memory Mapping 41.6.5.4. 4:2:2 Planar Mode Frame Buffer Memory Mapping 41.6.5.5. 4:2:0 Planar Mode Frame Buffer Memory Mapping 41.6.5.6. 4:2:0 Semiplanar Frame Buffer Memory Mapping 41.6.6. Chrominance Upsampling Unit 41.6.6.1. Chrominance Upsampling Algorithm 41.6.7. Line and Pixel Striding 41.6.7.1. Line Striding 41.6.7.2. Pixel Striding 41.6.8. Color Space Conversion Unit 41.6.9. Two-Dimension Scaler 41.6.9.1. Video Scaler Description 41.6.9.2. Horizontal Scaler 41.6.9.3. Vertical Scaler 41.6.10. Color Combine Unit 41.6.10.1. Window Overlay 41.6.10.2. Base Layer with Window Overlay Optimization 41.6.10.3. Overlay Blending 41.6.10.4. Window Blending 41.6.10.5. Color Keying 41.6.10.5.1. Source Color Keying 41.6.10.5.2. Destination Color Keying 41.6.11. LCDC PWM Controller 41.6.12. Post Processing Controller 41.6.13. LCD Overall Performance 41.6.13.1. Color Lookup Table (CLUT) 41.6.13.2. RGB Mode Fetch Performance 41.6.13.3. YUV Mode Fetch Performance 41.6.14. Input FIFO 41.6.15. Output FIFO 41.6.16. Output Timing Generation 41.6.16.1. Active Display Timing Mode 41.6.17. Output Format 41.6.17.1. Active Mode Output Pin Assignment 41.7. Register Summary 41.7.1. LCD Controller Configuration Register 0 41.7.2. LCD Controller Configuration Register 1 41.7.3. LCD Controller Configuration Register 2 41.7.4. LCD Controller Configuration Register 3 41.7.5. LCD Controller Configuration Register 4 41.7.6. LCD Controller Configuration Register 5 41.7.7. LCD Controller Configuration Register 6 41.7.8. LCD Controller Enable Register 41.7.9. LCD Controller Disable Register 41.7.10. LCD Controller Status Register 41.7.11. LCD Controller Interrupt Enable Register 41.7.12. LCD Controller Interrupt Disable Register 41.7.13. LCD Controller Interrupt Mask Register 41.7.14. LCD Controller Interrupt Status Register 41.7.15. LCD Controller Attribute Register 41.7.16. Base Layer Channel Enable Register 41.7.17. Base Layer Channel Disable Register 41.7.18. Base Layer Channel Status Register 41.7.19. Base Layer Interrupt Enable Register 41.7.20. Base Layer Interrupt Disable Register 41.7.21. Base Layer Interrupt Mask Register 41.7.22. Base Layer Interrupt Status Register 41.7.23. Base DMA Head Register 41.7.24. Base DMA Address Register 41.7.25. Base DMA Control Register 41.7.26. Base DMA Next Register 41.7.27. Base Layer Configuration Register 0 41.7.28. Base Layer Configuration Register 1 41.7.29. Base Layer Configuration Register 2 41.7.30. Base Layer Configuration Register 3 41.7.31. Base Layer Configuration Register 4 41.7.32. Base Layer Configuration Register 5 41.7.33. Base Layer Configuration Register 6 41.7.34. Overlay 1 Channel Enable Register 41.7.35. Overlay 1 Channel Disable Register 41.7.36. Overlay 1 Channel Status Register 41.7.37. Overlay 1 Interrupt Enable Register 41.7.38. Overlay 1 Interrupt Disable Register 41.7.39. Overlay 1 Interrupt Mask Register 41.7.40. Overlay 1 Interrupt Status Register 41.7.41. Overlay 1 Head Register 41.7.42. Overlay 1 Address Register 41.7.43. Overlay 1 Control Register 41.7.44. Overlay 1 Next Register 41.7.45. Overlay 1 Configuration Register 0 41.7.46. Overlay 1 Configuration Register 1 41.7.47. Overlay 1 Configuration Register 2 41.7.48. Overlay 1 Configuration Register 3 41.7.49. Overlay 1 Configuration Register 4 41.7.50. Overlay 1 Configuration Register 5 41.7.51. Overlay 1 Configuration Register 6 41.7.52. Overlay 1 Configuration Register 7 41.7.53. Overlay 1 Configuration Register 8 41.7.54. Overlay 1 Configuration Register 9 41.7.55. Overlay 2 Channel Enable Register 41.7.56. Overlay 2 Channel Disable Register 41.7.57. Overlay 2 Channel Status Register 41.7.58. Overlay 2 Interrupt Enable Register 41.7.59. Overlay 2 Interrupt Disable Register 41.7.60. Overlay 2 Interrupt Mask Register 41.7.61. Overlay 2 Interrupt Status Register 41.7.62. Overlay 2 Head Register 41.7.63. Overlay 2 Address Register 41.7.64. Overlay 2 Control Register 41.7.65. Overlay 2 Next Register 41.7.66. Overlay 2 Configuration Register 0 41.7.67. Overlay 2 Configuration Register 1 41.7.68. Overlay 2 Configuration Register 2 41.7.69. Overlay 2 Configuration Register 3 41.7.70. Overlay 2 Configuration Register 4 41.7.71. Overlay 2 Configuration Register 5 41.7.72. Overlay 2 Configuration Register 6 41.7.73. Overlay 2 Configuration Register 7 41.7.74. Overlay 2 Configuration Register 8 41.7.75. Overlay 2 Configuration Register 9 41.7.76. High-End Overlay Channel Enable Register 41.7.77. High-End Overlay Channel Disable Register 41.7.78. High-End Overlay Channel Status Register 41.7.79. High-End Overlay Interrupt Enable Register 41.7.80. High-End Overlay Interrupt Disable Register 41.7.81. High-End Overlay Interrupt Mask Register 41.7.82. High-End Overlay Interrupt Status Register 41.7.83. High-End Overlay DMA Head Register 41.7.84. High-End Overlay DMA Address Register 41.7.85. High-End Overlay DMA Control Register 41.7.86. High-End Overlay DMA Next Register 41.7.87. High-End Overlay U-UV DMA Head Register 41.7.88. High-End Overlay U-UV DMA Address Register 41.7.89. High-End Overlay U-UV DMA Control Register 41.7.90. High-End Overlay U-UV DMA Next Register 41.7.91. High-End Overlay V DMA Head Register 41.7.92. High-End Overlay V DMA Address Register 41.7.93. High-End Overlay V DMA Control Register 41.7.94. High-End Overlay V DMA Next Register 41.7.95. High-End Overlay Configuration Register 0 41.7.96. High-End Overlay Configuration Register 1 41.7.97. High-End Overlay Configuration Register 2 41.7.98. High-End Overlay Configuration Register 3 41.7.99. High-End Overlay Configuration Register 4 41.7.100. High-End Overlay Configuration Register 5 41.7.101. High-End Overlay Configuration Register 6 41.7.102. High-End Overlay Configuration Register 7 41.7.103. High-End Overlay Configuration Register 8 41.7.104. High-End Overlay Configuration Register 9 41.7.105. High-End Overlay Configuration Register 10 41.7.106. High-End Overlay Configuration Register 11 41.7.107. High-End Overlay Configuration Register 12 41.7.108. High-End Overlay Configuration Register 13 41.7.109. High-End Overlay Configuration Register 14 41.7.110. High-End Overlay Configuration Register 15 41.7.111. High-End Overlay Configuration Register 16 41.7.112. High-End Overlay Configuration Register 17 41.7.113. High-End Overlay Configuration Register 18 41.7.114. High-End Overlay Configuration Register 19 41.7.115. High-End Overlay Configuration Register 20 41.7.116. High-End Overlay Configuration Register 21 41.7.117. High-End Overlay Configuration Register 22 41.7.118. High-End Overlay Configuration Register 23 41.7.119. High-End Overlay Configuration Register 24 41.7.120. High-End Overlay Configuration Register 25 41.7.121. High-End Overlay Configuration Register 26 41.7.122. High-End Overlay Configuration Register 27 41.7.123. High-End Overlay Configuration Register 28 41.7.124. High-End Overlay Configuration Register 29 41.7.125. High-End Overlay Configuration Register 30 41.7.126. High-End Overlay Configuration Register 31 41.7.127. High-End Overlay Configuration Register 32 41.7.128. High-End Overlay Configuration Register 33 41.7.129. High-End Overlay Configuration Register 34 41.7.130. High-End Overlay Configuration Register 35 41.7.131. High-End Overlay Configuration Register 36 41.7.132. High-End Overlay Configuration Register 37 41.7.133. High-End Overlay Configuration Register 38 41.7.134. High-End Overlay Configuration Register 39 41.7.135. High-End Overlay Configuration Register 40 41.7.136. High-End Overlay Configuration Register 41 41.7.137. Post Processing Channel Enable Register 41.7.138. Post Processing Channel Disable Register 41.7.139. Post Processing Channel Status Register 41.7.140. Post Processing Interrupt Enable Register 41.7.141. Post Processing Interrupt Disable Register 41.7.142. Post Processing Interrupt Mask Register 41.7.143. Post Processing Interrupt Status Register 41.7.144. Post Processing Head Register 41.7.145. Post Processing Address Register 41.7.146. Post Processing Control Register 41.7.147. Post Processing Next Register 41.7.148. Post Processing Configuration Register 0 41.7.149. Post Processing Configuration Register 1 41.7.150. Post Processing Configuration Register 2 41.7.151. Post Processing Configuration Register 3 41.7.152. Post Processing Configuration Register 4 41.7.153. Post Processing Configuration Register 5 41.7.154. Base CLUT Register x 41.7.155. Overlay 1 CLUT Register x 41.7.156. Overlay 2 CLUT Register x 41.7.157. High-End Overlay CLUT Register x 42. Ethernet MAC (GMAC) 42.1. Description 42.2. Embedded Characteristics 42.3. Block Diagram 42.4. Signal Interfaces 42.5. Product Dependencies 42.5.1. I/O Lines 42.5.2. Power Management 42.5.3. Interrupt Sources 42.6. Functional Description 42.6.1. Media Access Controller 42.6.2. 1588 Timestamp Unit 42.6.3. Direct Memory Access Interface 42.6.3.1. Packet Buffer DMA 42.6.3.2. Receive Buffers 42.6.3.3. Transmit Buffers 42.6.3.4. DMA Bursting on the System Bus 42.6.3.5. DMA Packet Buffer 42.6.3.6. Transmit Packet Buffer 42.6.3.7. Receive Packet Buffer 42.6.3.8. Priority Queueing in the DMA 42.6.4. MAC Transmit Block 42.6.5. Transmit Scheduling Algorithm 42.6.5.1. Introduction 42.6.5.2. 802.1Qav Support - Credit-based Shaping 42.6.5.3. Fixed Priority 42.6.5.4. Deficit Weighted Round Robin (DWRR) 42.6.5.5. Enhanced Transmission Selection (ETS) 42.6.6. MAC Receive Block 42.6.7. Checksum Offload for IP, TCP and UDP 42.6.7.1. Receiver Checksum Offload 42.6.7.2. Transmitter Checksum Offload 42.6.8. MAC Filtering Block 42.6.9. Broadcast Address 42.6.10. Hash Addressing 42.6.11. Copy all Frames (Promiscuous Mode) 42.6.12. Disable Copy of Pause Frames 42.6.13. VLAN Support 42.6.14. Wake on LAN Support 42.6.15. IEEE 1588 Support 42.6.16. MAC 802.3 Pause Frame Support 42.6.16.1. 802.3 Pause Frame Reception 42.6.16.2. 802.3 Pause Frame Transmission 42.6.17. MAC PFC Priority-based Pause Frame Support 42.6.17.1. PFC Pause Frame Reception 42.6.17.2. PFC Pause Frame Transmission 42.6.18. Energy-efficient Ethernet Support 42.6.19. LPI Operation in the GMAC 42.6.20. PHY Interface 42.6.21. 10/100 Operation 42.6.22. Jumbo Frames 42.7. Programming Interface 42.7.1. Initialization 42.7.1.1. Configuration 42.7.1.2. Receive Buffer List 42.7.1.3. Transmit Buffer List 42.7.1.4. Address Matching 42.7.1.5. PHY Maintenance 42.7.1.6. Interrupts 42.7.1.7. Transmitting Frames 42.7.1.8. Receiving Frames 42.7.2. Statistics Registers 42.8. Register Summary 42.8.1. GMAC Network Control Register 42.8.2. GMAC Network Configuration Register 42.8.3. GMAC Network Status Register 42.8.4. GMAC User Register 42.8.5. GMAC DMA Configuration Register 42.8.6. GMAC Transmit Status Register 42.8.7. GMAC Receive Buffer Queue Base Address Register 42.8.8. GMAC Transmit Buffer Queue Base Address Register 42.8.9. GMAC Receive Status Register 42.8.10. GMAC Interrupt Status Register 42.8.11. GMAC Interrupt Enable Register 42.8.12. GMAC Interrupt Disable Register 42.8.13. GMAC Interrupt Mask Register 42.8.14. GMAC PHY Maintenance Register 42.8.15. GMAC Receive Pause Quantum Register 42.8.16. GMAC Transmit Pause Quantum Register 42.8.17. GMAC RX Jumbo Frame Max Length Register 42.8.18. GMAC_INTM 42.8.19. GMAC_SYSWT 42.8.20. GMAC Hash Register Bottom 42.8.21. GMAC Hash Register Top 42.8.22. GMAC Specific Address 1 Bottom Register 42.8.23. GMAC Specific Address 1 Top Register 42.8.24. GMAC Specific Address 2 Bottom Register 42.8.25. GMAC Specific Address 2 Top Register 42.8.26. GMAC Specific Address 3 Bottom Register 42.8.27. GMAC Specific Address 3 Top Register 42.8.28. GMAC Specific Address 4 Bottom Register 42.8.29. GMAC Specific Address 4 Top Register 42.8.30. GMAC Type ID Match 1 Register 42.8.31. GMAC Type ID Match 2 Register 42.8.32. GMAC Type ID Match 3 Register 42.8.33. GMAC Type ID Match 4 Register 42.8.34. GMAC Wake on LAN Register 42.8.35. GMAC IPG Stretch Register 42.8.36. GMAC Stacked VLAN Register 42.8.37. GMAC Transmit PFC Pause Register 42.8.38. GMAC Specific Address 1 Mask Bottom Register 42.8.39. GMAC Specific Address Mask 1 Top Register 42.8.40. Address Mask for RX Data Buffer Accesses Register 42.8.41. PTP RX Unicast IP Destination Address Register 42.8.42. PTP TX Unicast IP Destination Address Register 42.8.43. GMAC 1588 Timer Nanosecond Comparison Register 42.8.44. GMAC 1588 Timer Second Comparison Low Register 42.8.45. GMAC 1588 Timer Second Comparison High Register 42.8.46. GMAC PTP Event Frame Transmitted Seconds High Register 42.8.47. GMAC PTP Event Frame Received Seconds High Register 42.8.48. GMAC PTP Peer Event Frame Transmitted Seconds High Register 42.8.49. GMAC PTP Peer Event Frame Received Seconds High Register 42.8.50. GMAC Octets Transmitted Low Register 42.8.51. GMAC Octets Transmitted High Register 42.8.52. GMAC Frames Transmitted Register 42.8.53. GMAC Broadcast Frames Transmitted Register 42.8.54. GMAC Multicast Frames Transmitted Register 42.8.55. GMAC Pause Frames Transmitted Register 42.8.56. GMAC 64 Byte Frames Transmitted Register 42.8.57. GMAC 65 to 127 Byte Frames Transmitted Register 42.8.58. GMAC 128 to 255 Byte Frames Transmitted Register 42.8.59. GMAC 256 to 511 Byte Frames Transmitted Register 42.8.60. GMAC 512 to 1023 Byte Frames Transmitted Register 42.8.61. GMAC 1024 to 1518 Byte Frames Transmitted Register 42.8.62. GMAC Greater Than 1518 Byte Frames Transmitted Register 42.8.63. GMAC Transmit Underruns Register 42.8.64. GMAC Single Collision Frames Register 42.8.65. GMAC Multiple Collision Frames Register 42.8.66. GMAC Excessive Collisions Register 42.8.67. GMAC Late Collisions Register 42.8.68. GMAC Deferred Transmission Frames Register 42.8.69. GMAC Carrier Sense Errors Register 42.8.70. GMAC Octets Received Low Register 42.8.71. GMAC Octets Received High Register 42.8.72. GMAC Frames Received Register 42.8.73. GMAC Broadcast Frames Received Register 42.8.74. GMAC Multicast Frames Received Register 42.8.75. GMAC Pause Frames Received Register 42.8.76. GMAC 64 Byte Frames Received Register 42.8.77. GMAC 65 to 127 Byte Frames Received Register 42.8.78. GMAC 128 to 255 Byte Frames Received Register 42.8.79. GMAC 256 to 511 Byte Frames Received Register 42.8.80. GMAC 512 to 1023 Byte Frames Received Register 42.8.81. GMAC 1024 to 1518 Byte Frames Received Register 42.8.82. GMAC 1519 to Maximum Byte Frames Received Register 42.8.83. GMAC Undersized Frames Received Register 42.8.84. GMAC Oversized Frames Received Register 42.8.85. GMAC Jabbers Received Register 42.8.86. GMAC Frame Check Sequence Errors Register 42.8.87. GMAC Length Field Frame Errors Register 42.8.88. GMAC Receive Symbol Errors Register 42.8.89. GMAC Alignment Errors Register 42.8.90. GMAC Receive Resource Errors Register 42.8.91. GMAC Receive Overruns Register 42.8.92. GMAC IP Header Checksum Errors Register 42.8.93. GMAC TCP Checksum Errors Register 42.8.94. GMAC UDP Checksum Errors Register 42.8.95. GMAC_FLRXPCR 42.8.96. GMAC 1588 Timer Increment Sub-nanoseconds Register 42.8.97. GMAC 1588 Timer Seconds High Register 42.8.98. GMAC 1588 Timer Seconds Low Register 42.8.99. GMAC 1588 Timer Nanoseconds Register 42.8.100. GMAC 1588 Timer Adjust Register 42.8.101. GMAC 1588 Timer Increment Register 42.8.102. GMAC PTP Event Frame Transmitted Seconds Low Register 42.8.103. GMAC PTP Event Frame Transmitted Nanoseconds Register 42.8.104. GMAC PTP Event Frame Received Seconds Low Register 42.8.105. GMAC PTP Event Frame Received Nanoseconds Register 42.8.106. GMAC PTP Peer Event Frame Transmitted Seconds Low Register 42.8.107. GMAC PTP Peer Event Frame Transmitted Nanoseconds Register 42.8.108. GMAC PTP Peer Event Frame Received Seconds Low Register 42.8.109. GMAC PTP Peer Event Frame Received Nanoseconds Register 42.8.110. GMAC Received LPI Transitions 42.8.111. GMAC Received LPI Time 42.8.112. GMAC Transmit LPI Transitions 42.8.113. GMAC Transmit LPI Time 42.8.114. GMAC Interrupt Status Register Priority Queue x 42.8.115. GMAC Transmit Buffer Queue Base Address Register Priority Queue x 42.8.116. GMAC Receive Buffer Queue Base Address Register Priority Queue x 42.8.117. GMAC Receive Buffer Size Register Priority Queue x 42.8.118. GMAC Credit-Based Shaping Control Register 42.8.119. GMAC Credit-Based Shaping IdleSlope Register for Queue A 42.8.120. GMAC Credit-Based Shaping IdleSlope Register for Queue B 42.8.121. GMAC_TQUBA 42.8.122. GMAC_TXBDCTRL 42.8.123. GMAC_RXBDCTRL 42.8.124. GMAC_RQUBA 42.8.125. GMAC Screening Type 1 Register x Priority Queue 42.8.126. GMAC Screening Type 2 Register x Priority Queue 42.8.127. GMAC_TSCTL 42.8.128. GMAC_TQBWRL0 42.8.129. GMAC_TQSA 42.8.130. GMAC Interrupt Enable Register Priority Queue x 42.8.131. GMAC Interrupt Disable Register Priority Queue x 42.8.132. GMAC Interrupt Mask Register Priority Queue x 42.8.133. GMAC Screening Type 2 EtherType Register x 42.8.134. GMAC Screening Type 2 Compare Word 0 Register x 42.8.135. GMAC Screening Type 2 Compare Word 1 Register x 43. USB Device High Speed Port (UDPHS) 43.1. Description 43.2. Embedded Characteristics 43.3. Block Diagram 43.4. Typical Connection 43.5. Product Dependencies 43.5.1. Power Management 43.5.2. Interrupt Sources 43.6. Functional Description 43.6.1. UTMI Transceivers Sharing 43.6.2. USB V2.0 High Speed Device Port Introduction 43.6.3. USB V2.0 High Speed Transfer Types 43.6.4. USB Transfer Event Definitions 43.6.5. USB V2.0 High Speed BUS Transactions 43.6.6. Endpoint Configuration 43.6.7. DPRAM Management 43.6.8. Transfer With DMA 43.6.9. Transfer Without DMA 43.6.10. Handling Transactions with USB V2.0 Device Peripheral 43.6.10.1. Setup Transaction 43.6.10.2. NYET 43.6.10.3. Data IN 43.6.10.4. Data OUT 43.6.10.5. STALL 43.6.11. Speed Identification 43.6.12. USB V2.0 High Speed Global Interrupt 43.6.13. Endpoint Interrupts 43.6.14. Power Modes 43.6.14.1. Controlling Device States 43.6.14.2. Not Powered State 43.6.14.3. Entering Attached State 43.6.14.4. From Powered State to Default State (Reset) 43.6.14.5. From Default State to Address State (Address Assigned) 43.6.14.6. From Address State to Configured State (Device Configured) 43.6.14.7. Entering Suspend State (Bus Activity) 43.6.14.8. Receiving a Host Resume 43.6.14.9. Sending an External Resume 43.6.15. Test Mode 43.7. Register Summary 43.7.1. UDPHS Control Register 43.7.2. UDPHS Frame Number Register 43.7.3. UDPHS Interrupt Enable Register 43.7.4. UDPHS Interrupt Status Register 43.7.5. UDPHS Clear Interrupt Register 43.7.6. UDPHS Endpoints Reset Register 43.7.7. UDPHS Test Register 43.7.8. UDPHS Endpoint Configuration Register 43.7.9. UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints) 43.7.10. UDPHS Endpoint Control Enable Register (Isochronous Endpoints) 43.7.11. UDPHS Endpoint Control Disable Register (Control, Bulk, Interrupt Endpoints) 43.7.12. UDPHS Endpoint Control Disable Register (Isochronous Endpoint) 43.7.13. UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints) 43.7.14. UDPHS Endpoint Control Register (Isochronous Endpoint) 43.7.15. UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints) 43.7.16. UDPHS Endpoint Set Status Register (Isochronous Endpoint) 43.7.17. UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints) 43.7.18. UDPHS Endpoint Clear Status Register (Isochronous Endpoint) 43.7.19. UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints) 43.7.20. UDPHS Endpoint Status Register (Isochronous Endpoint) 43.7.21. UDPHS DMA Channel Transfer Descriptor 43.7.22. UDPHS DMA Next Descriptor Address Register 43.7.23. UDPHS DMA Channel Address Register 43.7.24. UDPHS DMA Channel Control Register 43.7.25. UDPHS DMA Channel Status Register 44. USB Host High Speed Port (UHPHS) 44.1. Description 44.2. Embedded Characteristics 44.3. Block Diagram 44.4. Typical Connection 44.5. Product Dependencies 44.5.1. I/O Lines 44.5.2. Power Management 44.5.3. Interrupt Sources 44.6. Functional Description 44.6.1. UTMI Transceivers Sharing 44.6.2. EHCI 44.6.3. OHCI 44.6.4. HSIC 44.7. Register Summary 44.7.1. UHPHS Host Controller Capability Register 44.7.2. UHPHS Host Controller Structural Parameters Register 44.7.3. UHPHS Host Controller Capability Parameters Register 44.7.4. UHPHS USB Command Register 44.7.5. UHPHS USB Status Register 44.7.6. UHPHS USB Interrupt Enable Register 44.7.7. UHPHS USB Frame Index Register 44.7.8. UHPHS Periodic Frame List Base Address Register 44.7.9. UHPHS Asynchronous List Address Register 44.7.10. UHPHS Configure Flag Register 44.7.11. UHPHS Port Status and Control Register 44.7.12. EHCI: REG06 - AHB Error Status 44.7.13. EHCI: REG07 - AHB Host Error Address 44.7.14. EHCI: REG08 - HSIC Enable/Disable 45. Audio Class D Amplifier (CLASSD) 45.1. Description 45.2. Embedded Characteristics 45.3. Block Diagram 45.4. Pin Name List 45.5. Product Dependencies 45.5.1. I/O Lines 45.5.2. Power Management 45.5.3. Interrupt 45.6. Functional Description 45.6.1. Interpolator 45.6.1.1. Clock Configuration 45.6.1.2. CLASSD Frequency Response 45.6.2. Equalizer 45.6.3. De-emphasis Filter Frequency Response 45.6.4. Attenuator and Recommended Input Levels 45.6.5. Pulse Width Modulator (PWM) 45.6.6. Application Schematics For Use Case Examples 45.6.7. Register Write Protection 45.7. Register Summary 45.7.1. CLASSD Control Register 45.7.2. CLASSD Mode Register 45.7.3. CLASSD Interpolator Mode Register 45.7.4. CLASSD Interpolator Status Register 45.7.5. CLASSD Transmit Holding Register 45.7.6. CLASSD Interrupt Enable Register 45.7.7. CLASSD Interrupt Disable Register 45.7.8. CLASSD Interrupt Mask Register 45.7.9. CLASSD Interrupt Status Register 45.7.10. CLASSD Write Protection Mode Register 46. Inter-IC Sound Controller (I2SC) 46.1. Description 46.2. Embedded Characteristics 46.3. Block Diagram 46.4. I/O Lines Description 46.5. Product Dependencies 46.5.1. I/O Lines 46.5.2. Power Management 46.5.3. Clocks 46.5.4. DMA Controller 46.5.5. Interrupt Sources 46.6. Functional Description 46.6.1. Initialization 46.6.2. Basic Operation 46.6.3. Host, Controller and Client Modes 46.6.4. I2S Reception and Transmission Sequence 46.6.5. Serial Clock and Word Select Generation 46.6.6. Mono 46.6.7. Holding Registers 46.6.8. DMA Controller Operation 46.6.9. Loopback Mode 46.6.10. Interrupts 46.7. I2SC Application Examples 46.8. Register Summary 46.8.1. I2SC Control Register 46.8.2. I2SC Mode Register 46.8.3. I2SC Status Register 46.8.4. I2SC Status Clear Register 46.8.5. I2SC Status Set Register 46.8.6. I2SC Interrupt Enable Register 46.8.7. I2SC Interrupt Disable Register 46.8.8. I2SC Interrupt Mask Register 46.8.9. I2SC Receiver Holding Register 46.8.10. I2SC Transmitter Holding Register 47. Synchronous Serial Controller (SSC) 47.1. Description 47.2. Embedded Characteristics 47.3. Block Diagram 47.4. Application Block Diagram 47.5. SSC Application Examples 47.6. Pin Name List 47.7. Product Dependencies 47.7.1. I/O Lines 47.7.2. Power Management 47.7.3. Interrupt 47.8. Functional Description 47.8.1. Clock Management 47.8.1.1. Clock Divider 47.8.1.2. Transmit Clock Management 47.8.1.3. Receive Clock Management 47.8.1.4. Serial Clock Ratio Considerations 47.8.2. Transmit Operations 47.8.3. Receive Operations 47.8.4. Start 47.8.5. Frame Synchronization 47.8.5.1. Frame Sync Data 47.8.5.2. Frame Sync Edge Detection 47.8.6. Receive Compare Modes 47.8.6.1. Compare Functions 47.8.7. Data Format 47.8.8. Loop Mode 47.8.9. Interrupt 47.8.10. Register Write Protection 47.9. Register Summary 47.9.1. SSC Control Register 47.9.2. SSC Clock Mode Register 47.9.3. SSC Receive Clock Mode Register 47.9.4. SSC Receive Frame Mode Register 47.9.5. SSC Transmit Clock Mode Register 47.9.6. SSC Transmit Frame Mode Register 47.9.7. SSC Receive Holding Register 47.9.8. SSC Transmit Holding Register 47.9.9. SSC Receive Synchronization Holding Register 47.9.10. SSC Transmit Synchronization Holding Register 47.9.11. SSC Receive Compare 0 Register 47.9.12. SSC Receive Compare 1 Register 47.9.13. SSC Status Register 47.9.14. SSC Interrupt Enable Register 47.9.15. SSC Interrupt Disable Register 47.9.16. SSC Interrupt Mask Register 47.9.17. SSC Write Protection Mode Register 47.9.18. SSC Write Protection Status Register 48. Two-wire Interface (TWIHS) 48.1. Description 48.2. Embedded Characteristics 48.3. List of Abbreviations 48.4. Block Diagram 48.4.1. I/O Lines Description 48.5. Product Dependencies 48.5.1. I/O Lines 48.5.2. Power Management 48.5.3. Interrupt Sources 48.6. Functional Description 48.6.1. Transfer Format 48.6.2. Modes of Operation 48.6.3. Host Mode 48.6.3.1. Definition 48.6.3.2. Programming Host Mode 48.6.3.3. Transfer Rate Clock Source 48.6.3.4. Host Transmitter Mode 48.6.3.5. Host Receiver Mode 48.6.3.6. Internal Address 48.6.3.6.1. 7-bit Client Addressing 48.6.3.6.2. 10-bit Client Addressing 48.6.3.7. Repeated Start 48.6.3.8. Bus Clear Command 48.6.3.9. Using the DMA Controller (DMAC) in Host Mode 48.6.3.9.1. Data Transmit with the DMA in Host Mode 48.6.3.9.2. Data Receive with the DMA in Host Mode 48.6.3.10. SMBus Mode 48.6.3.10.1. Packet Error Checking 48.6.3.10.2. Timeouts 48.6.3.11. SMBus Quick Command (Host Mode Only) 48.6.3.12. Alternative Command 48.6.3.13. Handling Errors in Alternative Command 48.6.3.14. Read/Write Flowcharts 48.6.4. Multi-Host Mode 48.6.4.1. Definition 48.6.4.2. Different Multi-Host Modes 48.6.4.2.1. TWIHS as Host Only 48.6.4.2.2. TWIHS as Host or Client 48.6.5. Client Mode 48.6.5.1. Definition 48.6.5.2. Programming Client Mode 48.6.5.3. Receiving Data 48.6.5.3.1. Read Sequence 48.6.5.3.2. Write Sequence 48.6.5.3.3. Clock Stretching Sequence 48.6.5.3.4. General Call 48.6.5.4. Data Transfer 48.6.5.4.1. Read Operation 48.6.5.4.2. Write Operation 48.6.5.4.3. General Call 48.6.5.4.4. Clock Stretching 48.6.5.4.4.1. Clock Stretching in Read Mode 48.6.5.4.4.2. Clock Stretching in Write Mode 48.6.5.4.5. Reversal after a Repeated Start 48.6.5.4.5.1. Reversal of Read to Write 48.6.5.4.5.2. Reversal of Write to Read 48.6.5.5. Using the DMA Controller (DMAC) in Client Mode 48.6.5.5.1. Data Transmit with the DMA in Client Mode 48.6.5.5.2. Data Receive with the DMA in Client Mode 48.6.5.6. SMBus Mode 48.6.5.6.1. Packet Error Checking 48.6.5.6.2. Timeouts 48.6.5.7. High-Speed Client Mode 48.6.5.7.1. Read/Write Operation 48.6.5.7.2. Usage 48.6.5.8. Alternative Command 48.6.5.9. Asynchronous Partial Wake-Up (SleepWalking) 48.6.5.10. Client Read Write Flowcharts 48.6.6. FIFOs 48.6.6.1. Overview 48.6.6.2. Sending Data with FIFO Enabled 48.6.6.3. Receiving Data with FIFO Enabled 48.6.6.4. Sending/Receiving with FIFO Enabled in Client Mode 48.6.6.5. Clearing/Flushing FIFOs 48.6.6.6. TXRDY and RXRDY Behavior 48.6.6.7. Single Data Mode 48.6.6.8. Multiple Data Mode 48.6.6.8.1. TXRDY and RXRDY Configuration 48.6.6.8.2. DMAC 48.6.6.9. Transmit FIFO Lock 48.6.6.10. FIFO Pointer Error 48.6.6.11. FIFO Thresholds 48.6.6.12. FIFO Flags 48.6.7. TWIHS Comparison Function on Received Character 48.6.8. Register Write Protection 48.7. Register Summary 48.7.1. TWIHS Control Register 48.7.2. TWIHS Control Register (FIFO_ENABLED) 48.7.3. TWIHS Host Mode Register 48.7.4. TWIHS Client Mode Register 48.7.5. TWIHS Internal Address Register 48.7.6. TWIHS Clock Waveform Generator Register 48.7.7. TWIHS Status Register 48.7.8. TWIHS Status Register (FIFO_ENABLED) 48.7.9. TWIHS SMBus Timing Register 48.7.10. TWIHS Alternative Command Register 48.7.11. TWIHS Filter Register 48.7.12. TWIHS Interrupt Enable Register 48.7.13. TWIHS Interrupt Disable Register 48.7.14. TWIHS Interrupt Mask Register 48.7.15. TWIHS Receive Holding Register 48.7.16. TWIHS Receive Holding Register (FIFO Enabled) 48.7.17. TWIHS SleepWalking Matching Register 48.7.18. TWIHS Transmit Holding Register 48.7.19. TWIHS Transmit Holding Register (FIFO Enabled) 48.7.20. TWIHS FIFO Mode Register 48.7.21. TWIHS FIFO Level Register 48.7.22. TWIHS FIFO Status Register 48.7.23. TWIHS FIFO Interrupt Enable Register 48.7.24. TWIHS FIFO Interrupt Disable Register 48.7.25. TWIHS FIFO Interrupt Mask Register 48.7.26. TWIHS Write Protection Mode Register 48.7.27. TWIHS Write Protection Status Register 49. Flexible Serial Communication Controller (FLEXCOM) 49.1. Description 49.2. Embedded Characteristics 49.2.1. USART/UART Characteristics 49.2.2. SPI Characteristics 49.2.3. TWI/SMBus Characteristics 49.3. Block Diagram 49.4. I/O Lines Description 49.5. Product Dependencies 49.5.1. I/O Lines 49.5.2. Power Management 49.5.3. Interrupt Sources 49.6. Register Accesses 49.7. USART Functional Description 49.7.1. Baud Rate Generator 49.7.1.1. Baud Rate in Asynchronous Mode 49.7.1.1.1. Baud Rate Calculation Example 49.7.1.2. Fractional Baud Rate in Asynchronous Mode 49.7.1.3. Baud Rate in Synchronous Mode or SPI Mode 49.7.1.4. Baud Rate in ISO 7816 Mode 49.7.2. Receiver and Transmitter Control 49.7.3. Synchronous and Asynchronous Modes 49.7.3.1. Transmitter Operations 49.7.3.2. Manchester Encoder 49.7.3.2.1. Drift Compensation 49.7.3.3. Asynchronous Receiver 49.7.3.4. Manchester Decoder 49.7.3.5. Radio Interface: Manchester Encoded USART Application 49.7.3.6. Synchronous Receiver 49.7.3.7. Receiver Operations 49.7.3.8. Parity 49.7.3.9. Multidrop Mode 49.7.3.10. Transmitter Timeguard 49.7.3.11. Receiver Timeout 49.7.3.12. Framing Error 49.7.3.13. Transmit Break 49.7.3.14. Receive Break 49.7.3.15. Hardware Handshaking 49.7.4. ISO7816 Mode 49.7.4.1. ISO7816 Mode Overview 49.7.4.2. Protocol T = 0 49.7.4.2.1. Receive Error Counter 49.7.4.2.2. Receive NACK Inhibit 49.7.4.2.3. Transmit Character Repetition 49.7.4.2.4. Disable Successive Receive NACK 49.7.4.3. Protocol T = 1 49.7.5. IrDA Mode 49.7.5.1. IrDA Modulation 49.7.5.2. IrDA Baud Rate 49.7.5.3. IrDA Demodulator 49.7.6. RS485 Mode 49.7.7. USART Comparison Function on Received Character 49.7.8. SPI Mode 49.7.8.1. Modes of Operation 49.7.8.2. Bit Rate 49.7.8.3. Data Transfer 49.7.8.4. Receiver and Transmitter Control 49.7.8.5. Character Transmission 49.7.8.6. Character Reception 49.7.8.7. Receiver Timeout 49.7.9. LIN Mode 49.7.9.1. Modes of Operation 49.7.9.2. Baud Rate Configuration 49.7.9.3. Receiver and Transmitter Control 49.7.9.4. Character Transmission 49.7.9.5. Character Reception 49.7.9.6. Header Transmission (Host Node Configuration) 49.7.9.7. Header Reception (Client Node Configuration) 49.7.9.8. Client Node Synchronization 49.7.9.9. Identifier Parity 49.7.9.10. Node Action 49.7.9.11. Response Data Length 49.7.9.12. Checksum 49.7.9.13. Frame Slot Mode 49.7.9.14. LIN Errors 49.7.9.14.1. Bit Error 49.7.9.14.2. Inconsistent Synch Field Error 49.7.9.14.3. Identifier Parity Error 49.7.9.14.4. Checksum Error 49.7.9.14.5. Client Not Responding Error 49.7.9.14.6. Synch Tolerance Error 49.7.9.14.7. Header Timeout Error 49.7.9.15. LIN Frame Handling 49.7.9.15.1. Host Node Configuration 49.7.9.15.2. Client Node Configuration 49.7.9.16. LIN Frame Handling with the DMAC 49.7.9.16.1. Host Node Configuration 49.7.9.16.2. Client Node Configuration 49.7.9.17. Wakeup Request 49.7.9.18. Bus Idle Timeout 49.7.10. Test Modes 49.7.10.1. Normal Mode 49.7.10.2. Automatic Echo Mode 49.7.10.3. Local Loopback Mode 49.7.10.4. Remote Loopback Mode 49.7.11. USART FIFOs 49.7.11.1. Overview 49.7.11.2. Sending Data with FIFO Enabled 49.7.11.3. Receiving Data with FIFO Enabled 49.7.11.4. Clearing/Flushing FIFOs 49.7.11.5. TXEMPTY, TXRDY and RXRDY Behavior 49.7.11.6. FIFO Single Data Access 49.7.11.6.1. DMAC 49.7.11.7. FIFO Multiple Data Access 49.7.11.7.1. TXRDY and RXRDY Configuration 49.7.11.7.2. DMAC 49.7.11.8. Transmit FIFO Lock 49.7.11.9. FIFO Pointer Error 49.7.11.10. FIFO Thresholds 49.7.11.11. FIFO Flags 49.7.12. USART Register Write Protection 49.8. SPI Functional Description 49.8.1. Modes of Operation 49.8.2. Data Transfer 49.8.3. Host Mode Operations 49.8.3.1. Host Mode Block Diagram 49.8.3.2. Host Mode Flowchart 49.8.3.3. Clock Generation 49.8.3.4. Transfer Delays 49.8.3.5. Peripheral Selection 49.8.3.6. SPI Direct Access Memory Controller (DMAC) 49.8.3.7. Peripheral Chip Select Decoding 49.8.3.8. Peripheral Deselection without DMA 49.8.3.9. Peripheral Deselection with DMA 49.8.3.10. Mode Fault Detection 49.8.4. SPI Client Mode 49.8.5. SPI Comparison Function on Received Character 49.8.6. SPI Asynchronous and Partial Wake-up 49.8.7. SPI FIFOs 49.8.7.1. Overview 49.8.7.2. Sending Data with FIFO Enabled 49.8.7.3. Receiving Data with FIFO Enabled 49.8.7.4. Clearing/Flushing FIFOs 49.8.7.5. TXEMPTY, TDRE and RDRF Behavior 49.8.7.6. SPI Single Data Access 49.8.7.6.1. DMAC 49.8.7.7. SPI Multiple Data Access 49.8.7.7.1. TDRE and RDRF Configuration 49.8.7.7.2. DMAC 49.8.7.8. FIFO Pointer Error 49.8.7.9. FIFO Thresholds 49.8.7.10. FIFO Flags 49.8.8. SPI Register Write Protection 49.8.9. Local Loopback Test Mode 49.9. TWI Functional Description 49.9.1. Transfer Format 49.9.1.1. Digital Filter 49.9.2. Modes of Operation 49.9.3. Host Mode 49.9.3.1. Definition 49.9.3.2. Programming Host Mode 49.9.3.3. Transfer Speed/Bit Rate 49.9.3.4. Host Transmitter Mode 49.9.3.5. Host Receiver Mode 49.9.3.6. Internal Address 49.9.3.6.1. 7-bit Client Addressing 49.9.3.6.2. 10-bit Client Addressing 49.9.3.7. Repeated Start 49.9.3.8. Bus Clear Command 49.9.3.9. SMBus Mode 49.9.3.9.1. Packet Error Checking 49.9.3.9.2. Timeouts 49.9.3.10. SMBus Quick Command (Host Mode Only) 49.9.3.11. Alternative Command 49.9.3.12. Handling Errors in Alternative Command 49.9.3.13. Read/Write Flowcharts 49.9.4. Multi-Host Mode 49.9.4.1. Definition 49.9.4.2. Different Multi-Host Modes 49.9.4.2.1. TWI as Host Only 49.9.4.2.2. TWI as Host or Client 49.9.5. Client Mode 49.9.5.1. Definition 49.9.5.2. Programming Client Mode 49.9.5.3. Receiving Data 49.9.5.3.1. Read Sequence 49.9.5.3.2. Write Sequence 49.9.5.3.3. Clock Stretching Sequence 49.9.5.3.4. General Call 49.9.5.4. Data Transfer 49.9.5.4.1. Read Operation 49.9.5.4.2. Write Operation 49.9.5.4.3. General Call 49.9.5.4.4. Clock Stretching 49.9.5.4.4.1. — Clock Stretching in Read Mode 49.9.5.4.4.2. — Clock Stretching in Write Mode 49.9.5.4.5. Reversal after a Repeated Start 49.9.5.4.5.1. — Reversal of Read to Write 49.9.5.4.5.2. — Reversal of Write to Read 49.9.5.4.6. SMBus Mode 49.9.5.4.6.1. — Packet Error Checking 49.9.5.4.6.2. — Timeouts 49.9.5.5. High-Speed Client Mode 49.9.5.5.1. Read/Write Operation 49.9.5.5.2. Usage 49.9.5.6. Alternative Command 49.9.5.7. TWI Asynchronous and Partial Wakeup 49.9.5.8. Client Read/Write Flowcharts 49.9.6. TWI FIFOs 49.9.6.1. Overview 49.9.6.2. Sending Data with FIFO Enabled 49.9.6.3. Receiving Data with FIFO Enabled 49.9.6.4. Sending/Receiving with FIFO Enabled in Client Mode 49.9.6.5. Clearing/Flushing FIFOs 49.9.6.6. TXRDY and RXRDY Behavior 49.9.6.7. TWI Single Data Access 49.9.6.8. TWI Multiple Data Access 49.9.6.8.1. TXRDY and RXRDY Configuration 49.9.6.8.2. DMAC 49.9.6.9. Transmit FIFO Lock 49.9.6.10. FIFO Pointer Error 49.9.6.11. FIFO Thresholds 49.9.6.12. FIFO Flags 49.9.7. TWI Comparison Function on Received Character 49.9.8. TWI Register Write Protection 49.10. Register Summary 49.10.1. FLEXCOM Mode Register 49.10.2. FLEXCOM Receive Holding Register 49.10.3. FLEXCOM Transmit Holding Register 49.10.4. USART Control Register 49.10.5. USART Control Register (SPI_MODE) 49.10.6. USART Mode Register 49.10.7. USART Mode Register (SPI_MODE) 49.10.8. USART Interrupt Enable Register 49.10.9. USART Interrupt Enable Register (SPI_MODE) 49.10.10. USART Interrupt Enable Register (LIN_MODE) 49.10.11. USART Interrupt Disable Register 49.10.12. USART Interrupt Disable Register (SPI_MODE) 49.10.13. USART Interrupt Disable Register (LIN_MODE) 49.10.14. USART Interrupt Mask Register 49.10.15. USART Interrupt Mask Register (SPI_MODE) 49.10.16. USART Interrupt Mask Register (LIN_MODE) 49.10.17. USART Channel Status Register 49.10.18. USART Channel Status Register (SPI_MODE) 49.10.19. USART Channel Status Register (LIN_MODE) 49.10.20. USART Receive Holding Register 49.10.21. USART Receive Holding Register (FIFO Multi Data) 49.10.22. USART Transmit Holding Register 49.10.23. USART Transmit Holding Register (FIFO Multi Data) 49.10.24. USART Baud Rate Generator Register 49.10.25. USART Receiver Timeout Register 49.10.26. USART Transmitter Timeguard Register 49.10.27. USART FI DI RATIO Register 49.10.28. USART Number of Errors Register 49.10.29. USART IrDA FILTER Register 49.10.30. USART Manchester Configuration Register 49.10.31. USART LIN Mode Register 49.10.32. USART LIN Identifier Register 49.10.33. USART LIN Baud Rate Register 49.10.34. USART Comparison Register 49.10.35. USART FIFO Mode Register 49.10.36. USART FIFO Level Register 49.10.37. USART FIFO Interrupt Enable Register 49.10.38. USART FIFO Interrupt Disable Register 49.10.39. USART FIFO Interrupt Mask Register 49.10.40. USART FIFO Event Status Register 49.10.41. USART Write Protection Mode Register 49.10.42. USART Write Protection Status Register 49.10.43. SPI Control Register 49.10.44. SPI Mode Register 49.10.45. SPI Receive Data Register 49.10.46. SPI Receive Data Register (FIFO Multiple Data, 8-bit) 49.10.47. SPI Receive Data Register (FIFO Multiple Data, 16-bit) 49.10.48. SPI Transmit Data Register 49.10.49. SPI Transmit Data Register (FIFO Multiple Data, 8- to 16-bit) 49.10.50. SPI Status Register 49.10.51. SPI Interrupt Enable Register 49.10.52. SPI Interrupt Disable Register 49.10.53. SPI Interrupt Mask Register 49.10.54. SPI Chip Select Register 49.10.55. SPI FIFO Mode Register 49.10.56. SPI FIFO Level Register 49.10.57. SPI Comparison Register 49.10.58. SPI Write Protection Mode Register 49.10.59. SPI Write Protection Status Register 49.10.60. TWI Control Register 49.10.61. TWI Control Register (FIFO_ENABLED) 49.10.62. TWI Host Mode Register 49.10.63. TWI Client Mode Register 49.10.64. TWI Internal Address Register 49.10.65. TWI Clock Waveform Generator Register 49.10.66. TWI Status Register 49.10.67. TWI Status Register (FIFO ENABLED) 49.10.68. TWI Interrupt Enable Register 49.10.69. TWI Interrupt Disable Register 49.10.70. TWI Interrupt Mask Register 49.10.71. TWI Receive Holding Register 49.10.72. TWI Receive Holding Register (FIFO Enabled) 49.10.73. TWI Transmit Holding Register 49.10.74. TWI Transmit Holding Register (FIFO Enabled) 49.10.75. TWI SMBus Timing Register 49.10.76. TWI Alternative Command Register 49.10.77. TWI Filter Register 49.10.78. TWI Matching Register 49.10.79. TWI FIFO Mode Register 49.10.80. TWI FIFO Level Register 49.10.81. TWI FIFO Status Register 49.10.82. TWI FIFO Interrupt Enable Register 49.10.83. TWI FIFO Interrupt Disable Register 49.10.84. TWI FIFO Interrupt Mask Register 49.10.85. TWI Write Protection Mode Register 49.10.86. TWI Write Protection Status Register 50. Universal Asynchronous Receiver Transmitter (UART) 50.1. Description 50.2. Embedded Characteristics 50.3. Block Diagram 50.4. Product Dependencies 50.4.1. I/O Lines 50.4.2. Power Management 50.4.3. Interrupt Sources 50.5. Functional Description 50.5.1. Baud Rate Generator 50.5.2. Receiver 50.5.2.1. Receiver Reset, Enable and Disable 50.5.2.2. Start Detection and Data Sampling 50.5.2.3. Receiver Ready 50.5.2.4. Receiver Overrun 50.5.2.5. Parity Error 50.5.2.6. Receiver Framing Error 50.5.2.7. Receiver Digital Filter 50.5.2.8. Receiver Time-out 50.5.3. Transmitter 50.5.3.1. Transmitter Reset, Enable and Disable 50.5.3.2. Transmit Format 50.5.3.3. Transmitter Control 50.5.4. DMA Support 50.5.5. Comparison Function on Received Character 50.5.6. Asynchronous and Partial Wake-Up 50.5.7. Register Write Protection 50.5.8. Test Modes 50.6. Register Summary 50.6.1. UART Control Register 50.6.2. UART Mode Register 50.6.3. UART Interrupt Enable Register 50.6.4. UART Interrupt Disable Register 50.6.5. UART Interrupt Mask Register 50.6.6. UART Interrupt Status Register 50.6.7. UART Receiver Holding Register 50.6.8. UART Transmit Holding Register 50.6.9. UART Baud Rate Generator Register 50.6.10. UART Comparison Register 50.6.11. UART Receiver Time-out Register 50.6.12. UART Write Protection Mode Register 51. Serial Peripheral Interface (SPI) 51.1. Description 51.2. Embedded Characteristics 51.3. Block Diagram 51.4. Application Block Diagram 51.5. Signal Description 51.6. Product Dependencies 51.6.1. I/O Lines 51.6.2. Power Management 51.6.3. Interrupt 51.6.4. Direct Memory Access Controller (DMAC) 51.7. Functional Description 51.7.1. Modes of Operation 51.7.2. Data Transfer 51.7.3. Host Mode Operations 51.7.3.1. Host Mode Block Diagram 51.7.3.2. Host Mode Flow Diagram 51.7.3.3. Clock Generation 51.7.3.4. Transfer Delays 51.7.3.5. Peripheral Selection 51.7.3.6. SPI Direct Access Memory Controller (DMAC) 51.7.3.7. Peripheral Chip Select Decoding 51.7.3.8. Peripheral Deselection without DMA 51.7.3.9. Peripheral Deselection with DMA 51.7.3.10. Mode Fault Detection 51.7.4. SPI Client Mode 51.7.5. SPI Comparison Function on Received Character 51.7.6. SPI Asynchronous and Partial Wake-Up 51.7.7. FIFOs 51.7.7.1. Overview 51.7.7.2. Sending Data with FIFO Enabled 51.7.7.3. Receiving Data with FIFO Enabled 51.7.7.4. Clearing/Flushing FIFOs 51.7.7.5. TXEMPTY, TDRE and RDRF Behavior 51.7.7.6. Single Data Mode 51.7.7.6.1. DMAC 51.7.7.7. Multiple Data Mode 51.7.7.7.1. TDRE and RDRF Configuration 51.7.7.7.2. DMAC 51.7.7.8. FIFO Pointer Error 51.7.7.9. FIFO Thresholds 51.7.7.10. FIFO Flags 51.7.8. Local Loopback Test Mode 51.7.9. Register Write Protection 51.8. Register Summary 51.8.1. SPI_CR 51.8.2. SPI_MR 51.8.3. SPI_RDR 51.8.4. SPI_RDR (FIFO_MULTI_DATA_8) 51.8.5. SPI_RDR (FIFO_MULTI_DATA_16) 51.8.6. SPI_TDR 51.8.7. SPI_TDR (FIFO_MULTI_DATA) 51.8.8. SPI_SR 51.8.9. SPI_IER 51.8.10. SPI_IDR 51.8.11. SPI_IMR 51.8.12. SPI_CSRx 51.8.13. SPI_FMR 51.8.14. SPI_FLR 51.8.15. SPI_CMPR 51.8.16. SPI_WPMR 51.8.17. SPI_WPSR 52. Quad Serial Peripheral Interface (QSPI) 52.1. Description 52.2. Embedded Characteristics 52.3. Block Diagram 52.4. Signal Description 52.5. Product Dependencies 52.5.1. I/O Lines 52.5.2. Power Management 52.5.3. Interrupt Sources 52.5.4. Direct Memory Access Controller (DMA) 52.6. Functional Description 52.6.1. Serial Clock Baud Rate 52.6.2. Serial Clock Phase and Polarity 52.6.3. Transfer Delays 52.6.4. QSPI SPI Mode 52.6.4.1. SPI Mode Operations 52.6.4.2. SPI Mode Block Diagram 52.6.4.3. SPI Mode Flow Diagram 52.6.4.4. Peripheral Deselection without DMA 52.6.4.5. Peripheral Deselection with DMA 52.6.5. QSPI Serial Memory Mode 52.6.5.1. Instruction Frame 52.6.5.2. Instruction Frame Transmission 52.6.5.3. Read Memory Transfer 52.6.5.4. Continuous Read Mode 52.6.5.5. Instruction Frame Transmission Examples 52.6.6. Scrambling/Unscrambling Function 52.6.6.1. Clearing Scrambling Keys On Embedded Flash Erase 52.6.7. Register Write Protection 52.6.8. SPI Local Loopback Test Mode 52.7. Register Summary 52.7.1. QSPI Control Register 52.7.2. QSPI Mode Register 52.7.3. QSPI Receive Data Register 52.7.4. QSPI Transmit Data Register 52.7.5. QSPI Status Register 52.7.6. QSPI Interrupt Enable Register 52.7.7. QSPI Interrupt Disable Register 52.7.8. QSPI Interrupt Mask Register 52.7.9. QSPI Serial Clock Register 52.7.10. QSPI Instruction Address Register 52.7.11. QSPI Instruction Code Register 52.7.12. QSPI Instruction Frame Register 52.7.13. QSPI Scrambling Mode Register 52.7.14. QSPI Scrambling Key Register 52.7.15. QSPI Write Protection Mode Register 52.7.16. QSPI Write Protection Status Register 53. Secure Digital MultiMedia Card Controller (SDMMC) 53.1. Description 53.2. Embedded Characteristics 53.3. Reference Documents 53.4. Block Diagram 53.5. Application Block Diagram 53.6. Pin Name List 53.7. Product Dependencies 53.7.1. I/O Lines 53.7.2. Power Management 53.7.3. Interrupt Sources 53.8. SD/SDIO Operating Mode 53.9. e.MMC Operating Mode 53.9.1. Boot Operation Mode 53.9.1.1. Boot Procedure, Processor Mode 53.9.1.2. Boot Procedure, SDMA Mode 53.9.1.3. Boot Procedure, ADMA Mode 53.10. SDR104 / HS200 Tuning 53.10.1. DLL and Sampling Point 53.10.2. Retuning Method 53.10.2.1. SDMMC Tuning Sequence 53.11. I/O Calibration 53.12. Register Summary 53.12.1. SDMMC SDMA System Address / Argument 2 Register 53.12.2. SDMMC Block Size Register 53.12.3. SDMMC Block Count Register 53.12.4. SDMMC Argument 1 Register 53.12.5. SDMMC Transfer Mode Register 53.12.6. SDMMC Command Register 53.12.7. SDMMC Response Register x 53.12.8. SDMMC Buffer Data Port Register 53.12.9. SDMMC Present State Register 53.12.10. SDMMC Host Control 1 Register (SD_SDIO) 53.12.11. SDMMC Host Control 1 Register (e.MMC) 53.12.12. SDMMC Power Control Register 53.12.13. SDMMC Block Gap Control Register (SD_SDIO) 53.12.14. SDMMC Block Gap Control Register (e.MMC) 53.12.15. SDMMC Wakeup Control Register (SD_SDIO) 53.12.16. SDMMC Clock Control Register 53.12.17. SDMMC Timeout Control Register 53.12.18. SDMMC Software Reset Register 53.12.19. SDMMC Normal Interrupt Status Register (SD_SDIO) 53.12.20. SDMMC Normal Interrupt Status Register (e.MMC) 53.12.21. SDMMC Error Interrupt Status Register (SD_SDIO) 53.12.22. SDMMC Error Interrupt Status Register (e.MMC) 53.12.23. SDMMC Normal Interrupt Status Enable Register (SD_SDIO) 53.12.24. SDMMC Normal Interrupt Status Enable Register (e.MMC) 53.12.25. SDMMC Error Interrupt Status Enable Register (SD_SDIO) 53.12.26. SDMMC Error Interrupt Status Enable Register (e.MMC) 53.12.27. SDMMC Normal Interrupt Signal Enable Register (SD_SDIO) 53.12.28. SDMMC Normal Interrupt Signal Enable Register (e.MMC) 53.12.29. SDMMC Error Interrupt Signal Enable Register (SD_SDIO) 53.12.30. SDMMC Error Interrupt Signal Enable Register (e.MMC) 53.12.31. SDMMC Auto CMD Error Status Register 53.12.32. SDMMC Host Control 2 Register (SD_SDIO) 53.12.33. SDMMC Host Control 2 Register (e.MMC) 53.12.34. SDMMC Capabilities 0 Register 53.12.35. SDMMC Capabilities 1 Register 53.12.36. SDMMC Maximum Current Capabilities Register 53.12.37. SDMMC Force Event Register for Auto CMD Error Status 53.12.38. SDMMC Force Event Register for Error Interrupt Status 53.12.39. SDMMC ADMA Error Status Register 53.12.40. SDMMC ADMA System Address Register 0 53.12.41. SDMMC Preset Value Register 53.12.42. SDMMC Slot Interrupt Status Register 53.12.43. SDMMC Host Controller Version Register 53.12.44. SDMMC Additional Present State Register 53.12.45. SDMMC e.MMC Control 1 Register 53.12.46. SDMMC e.MMC Control 2 Register 53.12.47. SDMMC AHB Control Register 53.12.48. SDMMC Clock Control 2 Register 53.12.49. SDMMC Retuning Control 1 Register 53.12.50. SDMMC Retuning Control 2 Register 53.12.51. SDMMC Retuning Counter Value Register 53.12.52. SDMMC Retuning Interrupt Status Enable Register 53.12.53. SDMMC Retuning Interrupt Signal Enable Register 53.12.54. SDMMC Retuning Interrupt Status Register 53.12.55. SDMMC Retuning Status Slots Register 53.12.56. SDMMC Tuning Control Register 53.12.57. SDMMC Capabilities Control Register 53.12.58. SDMMC Calibration Control Register 54. Image Sensor Controller (ISC) 54.1. Description 54.2. Embedded Characteristics 54.3. Block Diagram and Use Cases 54.3.1. Functional Diagrams 54.4. I/O Lines Description 54.4.1. Clock Domain Diagram 54.4.2. Typical Use Cases 54.5. Product Dependencies 54.5.1. I/O Lines 54.5.2. Power Management 54.5.3. Interrupt Sources 54.6. Functional Description 54.6.1. ISC Clock Management 54.6.1.1. Software Requirement 54.6.2. Parallel Interface Timing Description 54.6.3. BT.601/656/1120 Embedded Timing Synchronization Operation 54.6.4. Parallel Interface External Sensor Connections 54.6.4.1. YCbCr, 10-bit CCIR656 with Embedded Synchronization 54.6.4.2. YCbCr, 8-bit CCIR656 with Embedded Synchronization 54.6.4.3. Raw Bayer Parallel Interface 54.6.4.4. Monochrome Parallel Interface 54.6.5. Parallel Front End (PFE) Module 54.6.5.1. Update the ISC Profile 54.6.5.2. Software Requirements 54.6.6. White Balance (WB) Module 54.6.7. Color Filter Array (CFA) Interpolation Module 54.6.7.1. Frame Size Requirement when Edge Interpolation is Off, ISC_CFA_CFG.EITPOL Cleared 54.6.7.2. Frame Size Requirement when Edge Interpolation is On, ISC_CFA_CFG.EITPOL Set 54.6.7.3. Bayer Mode and Edge Interpolation Description 54.6.8. Color Correction (CC) Module 54.6.9. Gamma Curve (GAM) Module 54.6.10. Color Space Conversion (CSC) Module 54.6.11. Contrast, Brightness, Hue and Saturation 54.6.12. 4:4:4 To 4:2:2 Chrominance Horizontal Subsampler (SUB422) Module 54.6.13. 4:2:2 To 4:2:0 Chrominance Vertical Subsampler (SUB420) Module 54.6.14. Rounding, Limiting and Packing (RLP) Module 54.6.15. DMA Interface 54.6.15.1. Descriptor Memory Address Mapping 54.6.15.2. Descriptor Memory Mapping 54.6.15.3. Example: Memory Mapping for 16-bit Packed, DMA Interface IMODE = 1 at ISC_DAD0.AD0 Location 54.6.15.4. Example: Memory Mapping for 12-bit YC420SP, DMA Interface IMODE = 5 54.6.15.5. Example: Memory Mapping for 12-bit YC420P, DMA Interface IMODE = 6 54.6.16. Histogram Module 54.7. Register Summary 54.7.1. ISC Control Enable Register 54.7.2. ISC Control Disable Register 54.7.3. ISC Control Status Register 54.7.4. ISC Parallel Front End Configuration 0 Register 54.7.5. ISC Parallel Front End Configuration 1 Register 54.7.6. ISC Parallel Front End Configuration 2 Register 54.7.7. ISC Clock Enable Register 54.7.8. ISC Clock Disable Register 54.7.9. ISC Clock Status Register 54.7.10. ISC Clock Configuration Register 54.7.11. ISC Interrupt Enable Register 54.7.12. ISC Interrupt Disable Register 54.7.13. ISC Interrupt Mask Register 54.7.14. ISC Interrupt Status Register 54.7.15. ISC White Balance Control Register 54.7.16. ISC White Balance Configuration Register 54.7.17. ISC White Balance Offset for R, GR Register 54.7.18. ISC White Balance Offset for B and GB Register 54.7.19. ISC White Balance Gain for R, GR Register 54.7.20. ISC White Balance Gain for B, GB Register 54.7.21. ISC Color Filter Array Control Register 54.7.22. ISC Color Filter Array Configuration Register 54.7.23. ISC Color Correction Control Register 54.7.24. ISC Color Correction RR RG Register 54.7.25. ISC Color Correction RB OR Register 54.7.26. ISC Color Correction GR GG Register 54.7.27. ISC Color Correction GB OG Register 54.7.28. ISC Color Correction BR BG Register 54.7.29. ISC Color Correction BB OB Register 54.7.30. ISC Gamma Correction Control Register 54.7.31. ISC_GAM_BENTRYx 54.7.32. ISC Gamma Correction Green Entry Register x [x=0..63] 54.7.33. ISC Gamma Correction Red Entry Register x [x=0..63] 54.7.34. ISC Color Space Conversion Control Register 54.7.35. ISC Color Space Conversion YR YG Register 54.7.36. ISC Color Space Conversion YB OY Register 54.7.37. ISC Color Space Conversion CBR CBG Register 54.7.38. ISC Color Space Conversion CBB OCB Register 54.7.39. ISC Color Space Conversion CRR CRG Register 54.7.40. ISC Color Space Conversion CRB OCR Register 54.7.41. ISC Contrast And Brightness Control Register 54.7.42. ISC Contrast And Brightness Configuration Register 54.7.43. ISC Contrast And Brightness, Brightness Register 54.7.44. ISC Contrast And Brightness, Contrast Register 54.7.45. ISC Subsampling 4:4:4 to 4:2:2 Control Register 54.7.46. ISC Subsampling 4:4:4 to 4:2:2 Configuration Register 54.7.47. ISC Subsampling 4:2:2 to 4:2:0 Control Register 54.7.48. ISC Rounding, Limiting and Packing Configuration Register 54.7.49. ISC Histogram Control Register 54.7.50. ISC Histogram Configuration Register 54.7.51. ISC DMA Configuration Register 54.7.52. ISC DMA Control Register 54.7.53. ISC DMA Descriptor Address Register 54.7.54. ISC DMA Address 0 Register 54.7.55. ISC DMA Stride 0 Register 54.7.56. ISC DMA Address 1 Register 54.7.57. ISC DMA Stride 1 Register 54.7.58. ISC DMA Address 2 Register 54.7.59. ISC DMA Stride 2 Register 54.7.60. ISC Histogram Entry x [x=0..511] 55. Controller Area Network (MCAN) 55.1. Description 55.2. Embedded Characteristics 55.3. Block Diagram 55.4. Product Dependencies 55.4.1. I/O Lines 55.4.2. Power Management 55.4.3. Interrupt Sources 55.4.4. Address Configuration 55.5. Functional Description 55.5.1. Operating Modes 55.5.1.1. Software Initialization 55.5.1.2. Normal Operation 55.5.1.3. CAN FD Operation 55.5.1.4. Transmitter Delay Compensation 55.5.1.4.1. Description 55.5.1.4.2. Transmitter Delay Measurement 55.5.1.5. Restricted Operation Mode 55.5.1.6. Bus Monitoring Mode 55.5.1.7. Disabled Automatic Retransmission 55.5.1.7.1. Frame Transmission in DAR Mode 55.5.1.8. Power-down (Sleep Mode) 55.5.1.9. Test Modes 55.5.1.9.1. External Loop Back Mode 55.5.1.9.2. Internal Loop Back Mode 55.5.2. Timestamp Generation 55.5.3. Timeout Counter 55.5.4. Rx Handling 55.5.4.1. Acceptance Filtering 55.5.4.1.1. Range Filter 55.5.4.1.2. Filter for Specific IDs 55.5.4.1.3. Classic Bit Mask Filter 55.5.4.1.4. Standard Message ID Filtering 55.5.4.1.4.1. Extended Message ID Filtering 55.5.4.2. Rx FIFOs 55.5.4.2.1. Rx FIFO Blocking Mode 55.5.4.2.2. Rx FIFO Overwrite Mode 55.5.4.3. Dedicated Rx Buffers 55.5.4.3.1. Rx Buffer Handling 55.5.4.4. Debug on CAN Support 55.5.4.4.1. Filtering for Debug Messages 55.5.4.4.2. Debug Message Handling 55.5.5. Tx Handling 55.5.5.1. Transmit Pause 55.5.5.2. Dedicated Tx Buffers 55.5.5.3. Tx FIFO 55.5.5.4. Tx Queue 55.5.5.5. Mixed Dedicated Tx Buffers / Tx FIFO 55.5.5.6. Mixed Dedicated Tx Buffers / Tx Queue 55.5.5.7. Transmit Cancellation 55.5.5.8. Tx Event Handling 55.5.6. FIFO Acknowledge Handling 55.5.7. Message RAM 55.5.7.1. Message RAM Configuration 55.5.7.2. Rx Buffer and FIFO Element 55.5.7.3. Tx Buffer Element 55.5.7.4. Tx Event FIFO Element 55.5.7.5. Standard Message ID Filter Element 55.5.7.6. Extended Message ID Filter Element 55.5.8. Hardware Reset Description 55.5.9. Access to Reserved Register Addresses 55.6. Register Summary 55.6.1. MCAN Endian Register 55.6.2. MCAN Data Bit Timing and Prescaler Register 55.6.3. MCAN Test Register 55.6.4. MCAN RAM Watchdog Register 55.6.5. MCAN CC Control Register 55.6.6. MCAN Nominal Bit Timing and Prescaler Register 55.6.7. MCAN Timestamp Counter Configuration Register 55.6.8. MCAN Timestamp Counter Value Register 55.6.9. MCAN Timeout Counter Configuration Register 55.6.10. MCAN Timeout Counter Value Register 55.6.11. MCAN Error Counter Register 55.6.12. MCAN Protocol Status Register 55.6.13. MCAN Transmitter Delay Compensation Register 55.6.14. MCAN Interrupt Register 55.6.15. MCAN Interrupt Enable Register 55.6.16. MCAN Interrupt Line Select Register 55.6.17. MCAN Interrupt Line Enable 55.6.18. MCAN Global Filter Configuration 55.6.19. MCAN Standard ID Filter Configuration 55.6.20. MCAN Extended ID Filter Configuration 55.6.21. MCAN Extended ID AND Mask 55.6.22. MCAN High Priority Message Status 55.6.23. MCAN New Data 1 55.6.24. MCAN New Data 2 55.6.25. MCAN Receive FIFO 0 Configuration 55.6.26. MCAN Receive FIFO 0 Status 55.6.27. MCAN Receive FIFO 0 Acknowledge 55.6.28. MCAN Receive Buffer Configuration 55.6.29. MCAN Receive FIFO 1 Configuration 55.6.30. MCAN Receive FIFO 1 Status 55.6.31. MCAN Receive FIFO 1 Acknowledge 55.6.32. MCAN Receive Buffer / FIFO Element Size Configuration 55.6.33. MCAN Tx Buffer Configuration 55.6.34. MCAN Tx FIFO/Queue Status 55.6.35. MCAN Tx Buffer Element Size Configuration 55.6.36. MCAN Transmit Buffer Request Pending 55.6.37. MCAN Transmit Buffer Add Request 55.6.38. MCAN Transmit Buffer Cancellation Request 55.6.39. MCAN Transmit Buffer Transmission Occurred 55.6.40. MCAN Transmit Buffer Cancellation Finished 55.6.41. MCAN Transmit Buffer Transmission Interrupt Enable 55.6.42. MCAN Transmit Buffer Cancellation Finished Interrupt Enable 55.6.43. MCAN Transmit Event FIFO Configuration 55.6.44. MCAN Tx Event FIFO Status 55.6.45. MCAN Tx Event FIFO Acknowledge 55.6.46. MCAN_TSU_TSCFG 55.6.47. MCAN_TSU_TSS1 55.6.48. MCAN_TSU_TSS2 55.6.49. MCAN_TSU_TSx 55.6.50. MCAN_TSU_ATB 56. Timer Counter (TC) 56.1. Description 56.2. Embedded Characteristics 56.3. Block Diagram 56.4. Pin List 56.5. Product Dependencies 56.5.1. I/O Lines 56.5.2. Power Management 56.5.3. Interrupt Sources 56.5.4. Synchronization Inputs from PWM 56.5.5. Fault Output 56.6. Functional Description 56.6.1. Description 56.6.2. 32-bit Counter 56.6.3. Clock Selection 56.6.4. Clock Control 56.6.5. Operating Modes 56.6.6. Trigger Events 56.6.7. Trigger Conditions 56.6.8. Capture Mode 56.6.9. Capture Registers A and B 56.6.10. Transferring Timer Values with DMAC in Capture Mode 56.6.11. Waveform Mode 56.6.12. Waveform Selection 56.6.12.1. WAVSEL = 00 56.6.12.2. WAVSEL = 10 56.6.12.3. WAVSEL = 01 56.6.12.4. WAVSEL = 11 56.6.13. External Event/Trigger Conditions 56.6.14. Synchronization with PWM 56.6.15. Output Controller 56.6.16. Quadrature Decoder 56.6.16.1. Description 56.6.16.2. Input Preprocessing 56.6.16.3. Direction Status and Change Detection 56.6.16.4. Position and Rotation Measurement 56.6.16.5. Speed Measurement 56.6.16.6. Detecting a Missing Index Pulse 56.6.16.7. Detecting Contamination/Dust at Rotary Encoder Low Speed 56.6.16.8. Missing Pulse Detection and Autocorrection 56.6.17. 2-bit Gray Up/Down Counter for Stepper Motor 56.6.18. Fault Mode 56.6.19. Register Write Protection 56.7. Register Summary 56.7.1. TC Channel Control Register 56.7.2. TC Channel Mode Register: Capture Mode 56.7.3. TC Channel Mode Register: Waveform Mode 56.7.4. TC Stepper Motor Mode Register 56.7.5. TC Register AB 56.7.6. TC Counter Value Register 56.7.7. TC Register A 56.7.8. TC Register B 56.7.9. TC Register C 56.7.10. TC Interrupt Status Register 56.7.11. TC Interrupt Enable Register 56.7.12. TC Interrupt Disable Register 56.7.13. TC Interrupt Mask Register 56.7.14. TC Extended Mode Register 56.7.15. TC Block Control Register 56.7.16. TC Block Mode Register 56.7.17. TC QDEC Interrupt Enable Register 56.7.18. TC QDEC Interrupt Disable Register 56.7.19. TC QDEC Interrupt Mask Register 56.7.20. TC QDEC Interrupt Status Register 56.7.21. TC Fault Mode Register 56.7.22. TC Write Protection Mode Register 57. Pulse Density Modulation Interface Controller (PDMIC) 57.1. Description 57.2. Embedded Characteristics 57.3. Block Diagram 57.4. Signal Description 57.5. Product Dependencies 57.5.1. I/O Lines 57.5.2. Power Management 57.5.3. Interrupt Sources 57.6. Functional Description 57.6.1. PDM Interface 57.6.1.1. Description 57.6.1.2. Start-up Sequence 57.6.2. Digital Signal Processing (Digital Filter) 57.6.2.1. Description 57.6.2.2. Decimation Filter 57.6.2.3. Droop Compensation 57.6.2.4. Low Pass Filter 57.6.2.5. High Pass Filter 57.6.2.6. Gain and Offset Compensation 57.6.3. Conversion Results 57.6.4. Register Write Protection 57.7. Register Summary 57.7.1. PDMIC Control Register 57.7.2. PDMIC Mode Register 57.7.3. PDMIC Converted Data Register 57.7.4. PDMIC Interrupt Enable Register 57.7.5. PDMIC Interrupt Disable Register 57.7.6. PDMIC Interrupt Mask Register 57.7.7. PDMIC Interrupt Status Register 57.7.8. PDMIC DSP Configuration Register 0 57.7.9. PDMIC DSP Configuration Register 1 57.7.10. PDMIC Write Protection Mode Register 57.7.11. PDMIC Write Protection Status Register 58. Pulse Width Modulation Controller (PWM) 58.1. Description 58.2. Embedded Characteristics 58.3. Block Diagram 58.4. I/O Lines Description 58.5. Product Dependencies 58.5.1. I/O Lines 58.5.2. Power Management 58.5.3. Interrupt Sources 58.5.4. Fault Inputs 58.5.5. External Trigger Inputs 58.6. Functional Description 58.6.1. PWM Clock Generator 58.6.2. PWM Channel 58.6.2.1. Channel Block Diagram 58.6.2.2. Comparator 58.6.2.3. Trigger Selection for Timer Counter 58.6.2.3.1. Delay Measurement 58.6.2.3.2. Cumulated ON Time Measurement 58.6.2.4. 2-bit Gray Up/Down Counter for Stepper Motor 58.6.2.5. Dead-Time Generator 58.6.2.5.1. PWM Push-Pull Mode 58.6.2.6. Output Override 58.6.2.7. Fault Protection 58.6.2.7.1. Recoverable Fault 58.6.2.8. Spread Spectrum Counter 58.6.2.9. Synchronous Channels 58.6.2.9.1. Method 1: Manual write of duty-cycle values and manual trigger of the update 58.6.2.9.2. Method 2: Manual write of duty-cycle values and automatic trigger of the update 58.6.2.9.3. Method 3: Automatic write of duty-cycle values and automatic trigger of the update 58.6.2.10. Update Time for Double-Buffering Registers 58.6.3. PWM Comparison Units 58.6.4. PWM Event Lines 58.6.5. PWM External Trigger Mode 58.6.5.1. External PWM Reset Mode 58.6.5.1.1. Application Example 58.6.5.2. External PWM Start Mode 58.6.5.2.1. Application Example 58.6.5.3. Cycle-By-Cycle Duty Mode 58.6.5.3.1. Application Example 58.6.5.4. Leading-Edge Blanking (LEB) 58.6.6. PWM Controller Operations 58.6.6.1. Initialization 58.6.6.2. Source Clock Selection Criteria 58.6.6.3. Changing the Duty-Cycle, the Period and the Dead-Times 58.6.6.4. Changing the Update Period of Synchronous Channels 58.6.6.5. Changing the Comparison Value and the Comparison Configuration 58.6.6.6. Interrupt Sources 58.6.7. Register Write Protection 58.7. Register Summary 58.7.1. PWM Clock Register 58.7.2. PWM Enable Register 58.7.3. PWM Disable Register 58.7.4. PWM Status Register 58.7.5. PWM Interrupt Enable Register 1 58.7.6. PWM Interrupt Disable Register 1 58.7.7. PWM Interrupt Mask Register 1 58.7.8. PWM Interrupt Status Register 1 58.7.9. PWM Sync Channels Mode Register 58.7.10. PWM DMA Register 58.7.11. PWM Sync Channels Update Control Register 58.7.12. PWM Sync Channels Update Period Register 58.7.13. PWM Sync Channels Update Period Update Register 58.7.14. PWM Interrupt Enable Register 2 58.7.15. PWM Interrupt Disable Register 2 58.7.16. PWM Interrupt Mask Register 2 58.7.17. PWM Interrupt Status Register 2 58.7.18. PWM Output Override Value Register 58.7.19. PWM Output Selection Register 58.7.20. PWM Output Selection Set Register 58.7.21. PWM Output Selection Clear Register 58.7.22. PWM Output Selection Set Update Register 58.7.23. PWM Output Selection Clear Update Register 58.7.24. PWM Fault Mode Register 58.7.25. PWM Fault Status Register 58.7.26. PWM Fault Clear Register 58.7.27. PWM Fault Protection Value Register 1 58.7.28. PWM Fault Protection Enable Register 58.7.29. PWM Event Line x Mode Register 58.7.30. PWM Spread Spectrum Register 58.7.31. PWM Spread Spectrum Update Register 58.7.32. PWM Stepper Motor Mode Register 58.7.33. PWM Fault Protection Value Register 2 58.7.34. PWM Write Protection Control Register 58.7.35. PWM Write Protection Status Register 58.7.36. PWM Comparison x Value Register 58.7.37. PWM Comparison x Value Update Register 58.7.38. PWM Comparison x Mode Register 58.7.39. PWM Comparison x Mode Update Register 58.7.40. PWM Channel Mode Register 58.7.41. PWM Channel Duty Cycle Register 58.7.42. PWM Channel Duty Cycle Update Register 58.7.43. PWM Channel Period Register 58.7.44. PWM Channel Period Update Register 58.7.45. PWM Channel Counter Register 58.7.46. PWM Channel Dead Time Register 58.7.47. PWM Channel Dead Time Update Register 58.7.48. PWM Channel Mode Update Register 58.7.49. PWM External Trigger Register 58.7.50. PWM Leading-Edge Blanking Register 59. Secure Fuse Controller (SFC) 59.1. Description 59.2. Embedded Characteristics 59.3. Block Diagram 59.4. Functional Description 59.4.1. Accessing the SFC 59.4.2. Fuse Partitioning 59.4.3. Fuse Integrity Checking 59.4.4. Fuse Integrity Live Checking 59.4.5. Fuse Access 59.4.5.1. Fuse Reading 59.4.5.2. Fuse Programming 59.4.5.3. Fuse Masking 59.4.6. Fuse Functions 59.5. Register Summary 59.5.1. SFC Key Register 59.5.2. SFC Mode Register 59.5.3. SFC Interrupt Enable Register 59.5.4. SFC Interrupt Disable Register 59.5.5. SFC Interrupt Mask Register 59.5.6. SFC Status Register 59.5.7. SFC Data Register x 60. Integrity Check Monitor (ICM) 60.1. Description 60.2. Embedded Characteristics 60.3. Block Diagram 60.4. Product Dependencies 60.4.1. Power Management 60.4.2. Interrupt Sources 60.5. Functional Description 60.5.1. Overview 60.5.2. ICM Region Descriptor Structure 60.5.2.1. ICM_RADDR 60.5.2.2. ICM_RCFG 60.5.2.3. ICM_RCTRL 60.5.2.4. ICM_RNEXT 60.5.3. ICM Hash Area 60.5.3.1. Message Digest Example 60.5.4. Using ICM as SHA Engine 60.5.4.1. Settings for Simple SHA Calculation 60.5.4.2. Processing Period 60.5.5. ICM Automatic Monitoring Mode 60.5.6. Programming the ICM 60.5.7. Security Features 60.6. Register Summary 60.6.1. ICM Configuration Register 60.6.2. ICM Control Register 60.6.3. ICM Status Register 60.6.4. ICM Interrupt Enable Register 60.6.5. ICM Interrupt Disable Register 60.6.6. ICM Interrupt Mask Register 60.6.7. ICM Interrupt Status Register 60.6.8. ICM Undefined Access Status Register 60.6.9. ICM Descriptor Area Start Address Register 60.6.10. ICM Hash Area Start Address Register 60.6.11. ICM User Initial Hash Value Register 61. Advanced Encryption Standard Bridge (AESB) 61.1. Description 61.2. Embedded Characteristics 61.3. Product Dependencies 61.3.1. Power Management 61.3.2. Interrupt Sources 61.4. Functional Description 61.4.1. Operating Modes 61.4.2. Double Input Buffer 61.4.3. Start Modes 61.4.3.1. Manual Mode 61.4.3.2. Auto Mode 61.4.4. Last Output Data Mode 61.4.5. Manual and Auto Modes 61.4.5.1. If AESB_MR.LOD = 0 61.4.5.2. If AESB_MR.LOD = 1 61.4.6. Automatic Bridge Mode 61.4.6.1. Description 61.4.6.2. Configuration 61.4.7. Security Features 61.4.7.1. Unspecified Register Access Detection 61.5. Register Summary 61.5.1. AESB Control Register 61.5.2. AESB Mode Register 61.5.3. AESB Interrupt Enable Register 61.5.4. AESB Interrupt Disable Register 61.5.5. AESB Interrupt Mask Register 61.5.6. AESB Interrupt Status Register 61.5.7. AESB Key Word Register x 61.5.8. AESB Input Data Register x 61.5.9. AESB Output Data Register x 61.5.10. AESB Initialization Vector Register x 62. Advanced Encryption Standard (AES) 62.1. Description 62.2. Embedded Characteristics 62.3. Product Dependencies 62.3.1. Power Management 62.3.2. Interrupt Sources 62.4. Functional Description 62.4.1. AES Register Endianness 62.4.2. Operating Modes 62.4.3. Last Output Data Mode (CBC-MAC) 62.4.3.1. Manual and Auto Modes 62.4.3.1.1. If AES_MR.LOD = 0 62.4.3.1.2. If AES_MR.LOD = 1 62.4.3.2. DMA Mode 62.4.3.2.1. If AES_MR.LOD = 0 62.4.3.2.2. If AES_MR.LOD = 1 62.4.4. Galois/Counter Mode (GCM) 62.4.4.1. Description 62.4.4.2. Key Writing and Automatic Hash Subkey Calculation 62.4.4.3. GCM Processing 62.4.4.3.1. Processing a Complete Message with Tag Generation 62.4.4.3.2. Processing a Complete Message without Tag Generation 62.4.4.3.3. Processing a Fragmented Message without Tag Generation 62.4.4.3.4. Manual GCM Tag Generation 62.4.4.3.5. Processing a Message with only AAD (GHASHH) 62.4.4.3.6. Processing a Single GF128 Multiplication 62.4.5. XEX-based Tweaked-codebook Mode (XTS) 62.4.5.1. XTS Processing Procedure 62.4.5.1.1. Encrypted Tweak Generation 62.4.5.1.2. Data Processing 62.4.6. Double Input Buffer 62.4.7. Temporary Secured Storage for Keys 62.4.8. Start Modes 62.4.8.1. Manual Mode 62.4.8.2. Auto Mode 62.4.8.3. DMA Mode 62.4.9. Automatic Padding Mode 62.4.9.1. IPSec Padding 62.4.9.2. SSL Padding 62.4.9.3. Flags 62.4.10. Secure Protocol Layers Improved Performances 62.4.10.1. Cipher Mode 62.4.10.2. Decipher Mode 62.4.10.3. Encapsulating Security Payload (ESP) IPSec Examples 62.4.11. Security Features 62.4.11.1. Unspecified Register Access Detection 62.5. Register Summary 62.5.1. AES Control Register 62.5.2. AES Mode Register 62.5.3. AES Interrupt Enable Register 62.5.4. AES Interrupt Disable Register 62.5.5. AES Interrupt Mask Register 62.5.6. AES Interrupt Status Register 62.5.7. AES Key Word Register x 62.5.8. AES Input Data Register x 62.5.9. AES Output Data Register x 62.5.10. AES Initialization Vector Register x 62.5.11. AES Additional Authenticated Data Length Register 62.5.12. AES Plaintext/Ciphertext Length Register 62.5.13. AES GCM Intermediate Hash Word Register x 62.5.14. AES GCM Authentication Tag Word Register x 62.5.15. AES GCM Encryption Counter Value Register 62.5.16. AES GCM H Word Register x 62.5.17. AES Extended Mode Register 62.5.18. AES Byte Counter Register 62.5.19. AES Tweak Word Register x 62.5.20. AES Alpha Word Register x 63. Secure Hash Algorithm (SHA) 63.1. Description 63.2. Embedded Characteristics 63.3. Product Dependencies 63.3.1. Power Management 63.3.2. Interrupt Sources 63.4. Functional Description 63.4.1. SHA Algorithm 63.4.2. HMAC Algorithm 63.4.3. Processing Period 63.4.4. Double Input Buffer 63.4.5. Internal Registers for Initial Hash Value or Expected Hash Result 63.4.6. Automatic Padding 63.4.7. Automatic Check 63.4.8. Protocol Layers Improved Performances 63.4.9. Start Modes 63.4.9.1. Manual Mode 63.4.9.2. Auto Mode 63.4.9.3. DMA Mode 63.4.9.4. SHA Register Endianness 63.4.10. Security Features 63.4.10.1. Unspecified Register Access Detection 63.5. Register Summary 63.5.1. SHA Control Register 63.5.2. SHA Mode Register 63.5.3. SHA Interrupt Enable Register 63.5.4. SHA Interrupt Disable Register 63.5.5. SHA Interrupt Mask Register 63.5.6. SHA Interrupt Status Register 63.5.7. SHA Message Size Register 63.5.8. SHA Bytes Count Register 63.5.9. SHA Input Data Register x 63.5.10. SHA Input/Output Data Register x 64. Triple Data Encryption Standard (TDES) 64.1. Description 64.2. Embedded Characteristics 64.3. Product Dependencies 64.3.1. Power Management 64.3.2. Interrupt Sources 64.4. Functional Description 64.4.1. Operating Modes 64.4.2. Temporary Secured Storage for Keys 64.4.3. Start Modes 64.4.3.1. Manual Mode 64.4.3.2. Auto Mode 64.4.3.3. DMA Mode 64.4.4. Last Output Data Mode (CBC-MAC) 64.4.4.1. Manual and Auto Modes 64.4.4.1.1. TDES_MR.LOD = 0 64.4.4.1.2. TDES_MR.LOD = 1 64.4.4.2. DMA Mode 64.4.4.2.1. TDES_MR.LOD = 0 64.4.4.2.2. TDES_MR.LOD = 1 64.4.5. Security Features 64.4.5.1. Unspecified Register Access Detection 64.5. Register Summary 64.5.1. TDES Control Register 64.5.2. TDES Mode Register 64.5.3. TDES Interrupt Enable Register 64.5.4. TDES Interrupt Disable Register 64.5.5. TDES Interrupt Mask Register 64.5.6. TDES Interrupt Status Register 64.5.7. TDES Key 1 Word Register y 64.5.8. TDES Key 2 Word Register y 64.5.9. TDES Key 3 Word Register y 64.5.10. TDES Input Data Register x 64.5.11. TDES Output Data Register x 64.5.12. TDES Initialization Vector Register x 64.5.13. TDES XTEA Rounds Register 65. True Random Number Generator (TRNG) 65.1. Description 65.2. Embedded Characteristics 65.3. Block Diagram 65.4. Product Dependencies 65.4.1. Power Management 65.4.2. Interrupt Sources 65.5. Functional Description 65.5.1. First Value Read after Power-up 65.5.2. Entropy 65.6. Register Summary 65.6.1. TRNG Control Register 65.6.2. TRNG Interrupt Enable Register 65.6.3. TRNG Interrupt Disable Register 65.6.4. TRNG Interrupt Mask Register 65.6.5. TRNG Interrupt Status Register 65.6.6. TRNG Output Data Register 66. Analog Comparator Controller (ACC) 66.1. Description 66.2. Embedded Characteristics 66.3. Block Diagram 66.4. Signal Description 66.5. Product Dependencies 66.5.1. I/O Lines 66.5.2. Power Management 66.6. Functional Description 66.6.1. Description 66.6.2. Register Write Protection 66.7. Register Summary 66.7.1. ACC Control Register 66.7.2. ACC Mode Register 66.7.3. ACC Write Protection Mode Register 66.7.4. ACC Write Protection Status Register 67. Security Module (SECUMOD) 67.1. Description 67.2. Embedded Characteristics 67.3. Block Diagram 67.3.1. I/O Lines Description 67.4. Product Dependencies 67.4.1. Interrupt Sources 67.5. Functional Description 67.5.1. Memory Mapping 67.5.2. Scrambling Keys 67.5.3. Internal Random Number Generator (IRNG) 67.5.4. Protection Mechanisms 67.5.4.1. PIO Backup Controller 67.5.4.1.1. Output Mode 67.5.4.1.2. Input Mode 67.5.4.1.3. Static Intrusion Detectors and Programmable Internal Pull-up/Pull-down 67.5.4.1.4. Static Intrusion Detection 67.5.4.1.5. Internal Pull-up/Pull-down 67.5.4.1.6. Scheduled Pull-up/Pull-down 67.5.4.1.7. Debouncing Time 67.5.4.1.8. PIOBUx Alarm Filtering in Static Mode 67.5.4.2. JTAG Prevention 67.5.4.2.1. Debug Interface Access Prevention 67.5.4.2.2. Physical Restrictions for JTAG Debug Mode 67.5.4.2.3. Software Restrictions for JTAG Debug Mode 67.5.4.2.4. Software Prevention for JTAG Debug 67.5.5. Erasing Secure Memories 67.5.5.1. BUSRAM4KB Erase Sequence 67.5.5.1.1. Principle 67.5.5.2. BUREG256b Erase Sequence 67.5.5.3. During and After BUSRAM4KB and BUREG256b Erase Sequence 67.5.6. Operating Modes 67.5.6.1. Protection Unit 67.5.7. Activation or Deactivation of Protections 67.5.8. Power-Up Reset 67.6. Register Summary 67.6.1. SECUMOD Control Register 67.6.2. SECUMOD System Status Register 67.6.3. SECUMOD Status Register 67.6.4. SECUMOD_SCR 67.6.5. SECUMOD RAM Access Ready Register 67.6.6. SECUMOD PIO Backup Register x 67.6.7. SECUMOD JTAG Protection Control Register 67.6.8. SECUMOD Scrambling Key Register 67.6.9. SECUMOD RAM Access Rights Register 67.6.10. SECUMOD RAM Access Rights Status Register 67.6.11. SECUMOD Backup Mode Protection Register 67.6.12. SECUMOD_NMPR