The display memory size depends on the configured duty ratio. For 1/4 duty ratio the display memory is 44 bits wide per COM line. For 1/6 duty and 1/8 it is 42 bits and 40 bits wide respectively per COM line.
The CPU can access the display memory either through direct access or through indirect access.
With Direct access, the CPU can update the display memory by writing to the corresponding Segment's Data Low/ High for COMx Line register (SDATAL/Hx). For example, to update the segment connected to SEG4/COM2, write to bit 4 of the SDATAL2 register.
With In-direct access, the CPU can update the display memory by writing to the Indirect Segments Data Access register (ISDATA). This register allows to write up to eight contiguous bits in a single write operation to the display memory:
- SDATA[7:0] - segments data value (see the figure above)
- SDMASK[7:0] - mask for SDATA. When SDMASK[y]=1, SDATA[y] is not written to display memory.
- OFF[5:0] - byte offset in display memory (see the figure above)