Early Warning Interrupt Control
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EWOFFSET[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | x | x | x | x | |||||
Early Warning Interrupt Time Offset
These bits determine the number of GCLK_WDT clocks in the offset from the start of the watchdog time-out period to when the Early Warning interrupt is generated. These bits are loaded from NVM User Row at start-up. Refer to NVM User Row Mapping for more details.
| Value | Description |
|---|---|
| 0x0 | 8 clock cycles |
| 0x1 | 16 clock cycles |
| 0x2 | 32 clock cycles |
| 0x3 | 64 clock cycles |
| 0x4 | 128 clock cycles |
| 0x5 | 256 clocks cycles |
| 0x6 | 512 clocks cycles |
| 0x7 | 1024 clock cycles |
| 0x8 | 2048 clock cycles |
| 0x9 | 4096 clock cycles |
| 0xA | 8192 clock cycles |
| 0xB | 16384 clock cycles |
| 0xC-0xF | Reserved |