Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
PSZ[2:0] | |||||||||
Access | R | R | R | ||||||
Reset | x | x | x |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
NVMP[15:8] | |||||||||
Access | R | R | R | R | R | R | R | R | |
Reset | x | x | x | x | x | x | x | x |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
NVMP[7:0] | |||||||||
Access | R | R | R | R | R | R | R | R | |
Reset | x | x | x | x | x | x | x | x |
Page Size
Indicates the page size. Not all devices of the device families will provide all the page sizes indicated in the table.
Value | Name | Description |
---|---|---|
0x0 | 8 | 8 bytes |
0x1 | 16 | 16 bytes |
0x2 | 32 | 32 bytes |
0x3 | 64 | 64 bytes |
0x4 | 128 | 128 bytes |
0x5 | 256 | 256 bytes |
0x6 | 512 | 512 bytes |
0x7 | 1024 | 1024 bytes |
NVM Pages
Indicates the number of pages in the NVM main address space.