Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SYNCBUSY | |||||||||
Access | R | ||||||||
Reset | 0 |
Synchronization Busy
This bit is cleared when the synchronization of registers between clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.