Generic Clock Control
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
WRTLOCK | CLKEN | GEN[3:0] | |||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
ID[5:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Write Lock
When this bit is written, it will lock from further writes the generic clock pointed to by CLKCTRL.ID, the generic clock generator pointed to in CLKCTRL.GEN and the division factor used in the generic clock generator. It can only be unlocked by a power reset.
One exception to this is generic clock generator 0, which cannot be locked.
Value | Description |
---|---|
0 | The generic clock and the associated generic clock generator and division factor are not locked. |
1 | The generic clock and the associated generic clock generator and division factor are locked. |
Clock Enable
This bit is used to enable and disable a generic clock.
Value | Description |
---|---|
0 | The generic clock is disabled. |
1 | The generic clock is enabled. |
Generic Clock Generator
GEN[3:0] | Name | Description |
---|---|---|
0x0 | GCLKGEN0 | Generic clock generator 0 |
0x1 | GCLKGEN1 | Generic clock generator 1 |
0x2 | GCLKGEN2 | Generic clock generator 2 |
0x3 | GCLKGEN3 | Generic clock generator 3 |
0x4 | GCLKGEN4 | Generic clock generator 4 |
0x5 | GCLKGEN5 | Generic clock generator 5 |
0x6 | GCLKGEN6 | Generic clock generator 6 |
0x7 | GCLKGEN7 | Generic clock generator 7 |
0x8-0xF | Reserved | Reserved |
Generic Clock Selection ID
These bits select the generic clock that will be configured. The value of the ID bit group versus module instance is shown in the table below.
A power reset will reset the CLKCTRL register for all IDs, including the RTC. If the WRTLOCK bit of the corresponding ID is zero and the ID is not the RTC, a user reset will reset the CLKCTRL register for this ID.
After a power reset, the reset value of the CLKCTRL register versus module instance is as shown in the next table.
Module Instance | Reset Value after Power Reset | ||
---|---|---|---|
CLKCTRL.GEN | CLKCTRL.CLKEN | CLKCTRL.WRTLOCK | |
RTC | 0x00 | 0x00 | 0x00 |
WDT | 0x02 | 0x01 if WDT Enable bit in NVM User Row written to one 0x00 if WDT Enable bit in NVM User Row written to zero | 0x01 if WDT Always-On bit in NVM User Row written to one 0x00 if WDT Always-On bit in NVM User Row written to zero |
Others | 0x00 | 0x00 | 0x00 |
After a user reset, the reset value of the CLKCTRL register versus module instance is as shown in the table below.
Module Instance | Reset Value after a User Reset | ||
---|---|---|---|
CLKCTRL.GEN | CLCTRL.CLKEN | CLKCTRL.WRTLOCK | |
RTC | 0x00 if WRTLOCK=0 and CLKEN=0 No change if WRTLOCK=1 or CLKEN=1 | 0x00 if WRTLOCK=0 and CLKEN=0 No change if WRTLOCK=1 or CLKEN=1 | No change |
WDT | 0x02 if WRTLOCK=0 No change if WRTLOCK=1 | If WRTLOCK=0 0x01 if WDT Enable bit in NVM User Row written to one 0x00 if WDT Enable bit in NVM User Row written to zero If WRTLOCK=1 no change | No change |
Others | 0x00 if WRTLOCK=0 No change if WRTLOCK=1 | 0x00 if WRTLOCK=0 No change if WRTLOCK=1 | No change |
Value | Name | Description |
---|---|---|
0x00 | GCLK_DFLL48M_REF | DFLL48M Reference |
0x01 | GCLK_WDT | WDT |
0x02 | GCLK_RTC | RTC |
0x03 | GCLK_EIC | EIC |
0x04 | GCLK_EVSYS_CHANNEL_0 | EVSYS_CHANNEL_0 |
0x05 | GCLK_EVSYS_CHANNEL_1 | EVSYS_CHANNEL_1 |
0x06 | GCLK_EVSYS_CHANNEL_2 | EVSYS_CHANNEL_2 |
0x07 | GCLK_EVSYS_CHANNEL_3 | EVSYS_CHANNEL_3 |
0x08 | GCLK_EVSYS_CHANNEL_4 | EVSYS_CHANNEL_4 |
0x09 | GCLK_EVSYS_CHANNEL_5 | EVSYS_CHANNEL_5 |
0x0A | GCLK_EVSYS_CHANNEL_6 | EVSYS_CHANNEL_6 |
0x0B | GCLK_EVSYS_CHANNEL_7 | EVSYS_CHANNEL_7 |
0x0C | GCLK_SERCOMx_SLOW | SERCOMx_SLOW |
0x0D | GCLK_SERCOM0_CORE | SERCOM0_CORE |
0x0E | GCLK_SERCOM1_CORE | SERCOM1_CORE |
0x0F | GCLK_SERCOM2_CORE | SERCOM2_CORE |
0x10 | GCLK_SERCOM3_CORE | SERCOM3_CORE |
0x11 | GCLK_SERCOM4_CORE | SERCOM4_CORE |
0x12 | GCLK_SERCOM5_CORE | SERCOM5_CORE |
0x13 | GCLK_TC0, GCLK_TC1 | TC0, TC1 |
0x14 | GCLK_TC2, GCLK_TC3 | TC2, TC3 |
0x15 | GCLK_TC4, GCLK_TC5 | TC4, TC5 |
0x16 | GCLK_TC6, GCLK_TC7 | TC6, TC7 |
0x17 | GCLK_ADC | ADC |
0x18 | GCLK_AC_DIG | AC_DIG |
0x19 | GCLK_AC_ANA | AC_ANA |
0x1A | GCLK_DAC | DAC |
0x1B | GCLK_PTC | PTC |
0x1C-0x3F | - | Reserved |