On any reset the synchronous clocks start to their initial state:
- OSC8M is enabled and divided by 8
- Generic Generator 0 uses OSC8M as
source and generates GCLK_MAIN
- CPU and BUS clocks are undivided
On a Power Reset, the GCLK module starts to
its initial state:
- All Generic Clock Generators are
disabled except
- Generator 0 is using OSC8M as source without division and generates
GCLK_MAIN
- Generator 2 uses OSCULP32K as source without division
- All Generic Clocks are disabled
except:
- WDT Generic Clock uses the Generator 2 as source
On a User Reset the GCLK module starts to its initial state, except for:
- Generic Clocks that are write-locked ,
i.e., the according WRTLOCK is set to 1 prior to Reset or WDT Generic Clock if the WDT
Always-On at power on bit set in the NVM User Row
- Generic Clock is dedicated to the RTC
if the RTC Generic Clock is enabled
On any reset the clock sources are reset to their initial state except the 32KHz clock sources which are reset only by a power reset.