Channel Status
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CHBUSYn | CHBUSYn | CHBUSYn | CHBUSYn | CHBUSYn | CHBUSYn | CHBUSYn | CHBUSYn | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| USRRDYn | USRRDYn | USRRDYn | USRRDYn | USRRDYn | USRRDYn | USRRDYn | USRRDYn | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Channel n Busy [n=7..0]
This bit is cleared when channel n is idle
This bit is set if an event on channel n has not been handled by all event users connected to channel n.
Channel n User Ready [n=7..0]
This bit is cleared when at least one of the event users connected to the channel is not ready.
This bit is set when all event users connected to channel n are ready to handle incoming events on channel n.