INTENSET

Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
  0x10 8 PAC Write-Protection 0x00  
Parent topic: Register Description

Interrupt Enable Set

Bit  7 6 5 4 3 2 1 0  
              ERROR READY  
Access              R/W R/W  
Reset              0 0  

Bit 1 – ERROR: Error Interrupt Enable

Error Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit sets the ERROR interrupt enable.

This bit will read as the current value of the ERROR interrupt enable.

Bit 0 – READY: NVM Ready Interrupt Enable

NVM Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit sets the READY interrupt enable.

This bit will read as the current value of the READY interrupt enable.