This register allows the
user to configure one or more I/O pins as an input or output. This register can be
manipulated without doing a read-modify-write operation by using the Data Direction Toggle
(DIRTGL), Data Direction Clear (DIRCLR) and Data Direction Set (DIRSET) registers.
Tip: The I/O pins are
assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the
PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers,
with a 0x80 address spacing. For example, the register address offset for the Data
Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register
address offset for the DIR register for group 1 (PB00 to PB31) is 0x80.
|
0x00 |
32 |
PAC Write-Protection |
0x00000000 |
|
Port Data Direction
These bits set the data direction for the
individual I/O pins in the PORT group.
Value | Description |
---|
0 |
The corresponding I/O pin in the PORT
group is configured as an input. |
1 |
The corresponding I/O pin in the PORT
group is configured as an output. |