This register allows the
user to set one or more I/O pins as an output, without doing a read-modify-write operation.
Changes in this register will also be reflected in the Data Direction (DIR), Data Direction
Toggle (DIRTGL) and Data Direction Clear (DIRCLR) registers.
Tip: The I/O pins are
assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the
PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers,
with a 0x80 address spacing. For example, the register address offset for the Data
Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register
address offset for the DIR register for group 1 (PB00 to PB31) is 0x80.
|
0x08 |
32 |
PAC Write-Protection |
0x00000000 |
|
Port Data Direction Set
Writing
'0' to a bit has no effect.
Writing '1' to a bit will set the corresponding bit
in the DIR register, which configures the I/O pin as an output.
Value | Description |
---|
0 |
The corresponding I/O pin in the PORT
group will keep its configuration. |
1 |
The corresponding I/O pin in the PORT
group is configured as an output. |