Interrupt Flag Status and Clear - MODE0
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OVF | SYNCRDY | CMP0 | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Overflow
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.
Synchronization Ready
This flag is cleared by writing a one to the flag.
This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY), except when caused by enable or software reset, and an interrupt request will be generated if INTENCLR/SET.SYNCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Synchronization Ready interrupt flag.
Compare 0
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request will be generated if INTENCLR/SET.CMP0 is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Compare 0 interrupt flag.