PCLKSR

Power and Clocks Status

  0x0C 32 - 0x00000000  
Parent topic: Register Description

Power and Clocks Status

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
          B33SRDY BOD33DET BOD33RDY DFLLRCS  
Access          R R R R  
Reset          0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY  
Access  R R R R R R R R  
Reset  0 0 0 0 0 0 0 0  

Bit 11 – B33SRDY: BOD33 Synchronization Ready

BOD33 Synchronization Ready

ValueDescription
0 BOD33 synchronization is complete.
1 BOD33 synchronization is ongoing.

Bit 10 – BOD33DET: BOD33 Detection

BOD33 Detection

ValueDescription
0 No BOD33 detection.
1 BOD33 has detected that the I/O power supply is going below the BOD33 reference value.

Bit 9 – BOD33RDY: BOD33 Ready

BOD33 Ready

ValueDescription
0 BOD33 is not ready.
1 BOD33 is ready.

Bit 8 – DFLLRCS: DFLL Reference Clock Stopped

DFLL Reference Clock Stopped

ValueDescription
0 DFLL reference clock is running.
1 DFLL reference clock has stopped.

Bit 7 – DFLLLCKC: DFLL Lock Coarse

DFLL Lock Coarse

ValueDescription
0 No DFLL coarse lock detected.
1 DFLL coarse lock detected.

Bit 6 – DFLLLCKF: DFLL Lock Fine

DFLL Lock Fine

ValueDescription
0 No DFLL fine lock detected.
1 DFLL fine lock detected.

Bit 5 – DFLLOOB: DFLL Out Of Bounds

DFLL Out Of Bounds

ValueDescription
0 No DFLL Out Of Bounds detected.
1 DFLL Out Of Bounds detected.

Bit 4 – DFLLRDY: DFLL Ready

DFLL Ready

This bit is cleared when the synchronization of registers between clock domains is complete.

This bit is set when the synchronization of registers between clock domains is started.

ValueDescription
0 The Synchronization is ongoing.
1 The Synchronization is complete.

Bit 3 – OSC8MRDY: OSC8M Ready

OSC8M Ready

ValueDescription
0 OSC8M is not ready.
1 OSC8M is stable and ready to be used as a clock source.

Bit 2 – OSC32KRDY: OSC32K Ready

OSC32K Ready

ValueDescription
0 OSC32K is not ready.
1 OSC32K is stable and ready to be used as a clock source.

Bit 1 – XOSC32KRDY: XOSC32K Ready

XOSC32K Ready

ValueDescription
0 XOSC32K is not ready.
1 XOSC32K is stable and ready to be used as a clock source.

Bit 0 – XOSCRDY: XOSC Ready

XOSC Ready

ValueDescription
0 XOSC is not ready.
1 XOSC is stable and ready to be used as a clock source.