| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IDLE[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
Idle Mode Configuration
These bits select the Idle mode configuration after a WFI instruction.
| IDLE[1:0] | Name | Description |
|---|---|---|
| 0x0 | CPU | The CPU clock domain is stopped |
| 0x1 | AHB | The CPU and AHB clock domains are stopped |
| 0x2 | APB | The CPU, AHB and APB clock domains are stopped |
| 0x3 | Reserved |