Interrupt Enable Clear
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SYNCRDY | WINMON | OVERRUN | RESRDY | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Synchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Synchronization Ready interrupt is disabled. |
| 1 | The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the Synchronization Ready interrupt flag is set. |
Window Monitor Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Window Monitor Interrupt Enable bit and the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The window monitor interrupt is disabled. |
| 1 | The window monitor interrupt is enabled, and an interrupt request will be generated when the Window Monitor interrupt flag is set. |
Overrun Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Interrupt Enable bit and the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Overrun interrupt is disabled. |
| 1 | The Overrun interrupt is enabled, and an interrupt request will be generated when the Overrun interrupt flag is set. |
Result Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Result Ready Interrupt Enable bit and the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Result Ready interrupt is disabled. |
| 1 | The Result Ready interrupt is enabled, and an interrupt request will be generated when the Result Ready interrupt flag is set. |