- 32-bit AHB interface for reads and
writes
- All NVM sections are memory mapped to the AHB, including calibration and system configuration
- 32-bit APB interface for commands and control
- Programmable wait states for read optimization
- 16 regions can be individually
protected or unprotected
- Additional protection for boot loader
- Supports device protection through a security bit
- Interface to Power Manager for
power-down of Flash blocks in sleep modes
- Can optionally wake up on exit from
sleep or on first access
- Direct-mapped cache
Note: A register with property "Enable-Protected" may contain bits that are
not enable-protected.