Cortex-M0+ Peripherals
- System Control Space (SCS)
- The processor provides debug
through registers in the SCS. Refer to the Cortex-M0+ Technical Reference Manual
for details (www.arm.com).
- System Timer (SysTick)
- The System Timer is a 24-bit timer
clocked by CLK_CPU that extends the functionality of both the processor and the
NVIC. Refer to the Cortex-M0+ Technical Reference Manual for details (www.arm.com).
- Nested Vectored Interrupt Controller
(NVIC)
- External interrupt signals connect
to the NVIC, and the NVIC prioritizes the interrupts. Software can set the
priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely
coupled, providing low latency interrupt processing and efficient processing of
late arriving interrupts. Refer to Nested Vector Interrupt Controller and the Cortex-M0+ Technical Reference Manual for details
(www.arm.com).
- System Control Block (SCB)
- The System Control Block provides system implementation information, and system
control. This includes configuration, control, and reporting of the system
exceptions. Refer to the Cortex-M0+ Devices Generic User Guide for details (www.arm.com).