This register allows the
user to set one or more output I/O pin drive levels high, without doing a read-modify-write
operation. Changes in this register will also be reflected in the Data Output Value (OUT),
Data Output Value Toggle (OUTTGL) and Data Output Value Clear (OUTCLR) registers.
Tip: The I/O pins are
assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the
PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers,
with a 0x80 address spacing. For example, the register address offset for the Data
Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register
address offset for the DIR register for group 1 (PB00 to PB31) is 0x80.
|
0x18 |
32 |
PAC Write-Protection |
0x00000000 |
|
PORT Data Output Value Set
Writing
'0' to a bit has no effect.
Writing '1' to a bit will set the corresponding bit
in the OUT register, which sets the output drive level high for I/O pins configured as
outputs via the Data Direction register (DIR). For pins configured as inputs via Data
Direction register (DIR) with pull enabled via the Pull Enable register (PULLEN), these
bits will set the input pull direction to an internal pull-up.
Value | Description |
---|
0 |
The corresponding I/O pin in the
group will keep its configuration. |
1 |
The corresponding I/O pin output is
driven high, or the input is connected to an internal
pull-up. |