INTENCLR

Interrupt Enable Clear

  0x00 32 Write-Protected 0x00000000  
Parent topic: Register Description

Interrupt Enable Clear

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
          B33SRDY BOD33DET BOD33RDY DFLLRCS  
Access          R/W R/W R/W R/W  
Reset          0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bit 11 – B33SRDY: BOD33 Synchronization Ready Interrupt Enable

BOD33 Synchronization Ready Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the BOD33 Synchronization Ready Interrupt Enable bit, which disables the BOD33 Synchronization Ready interrupt.

ValueDescription
0 The BOD33 Synchronization Ready interrupt is disabled.
1 The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Synchronization Ready Interrupt flag is set.

Bit 10 – BOD33DET: BOD33 Detection Interrupt Enable

BOD33 Detection Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the BOD33 Detection Interrupt Enable bit, which disables the BOD33 Detection interrupt.

ValueDescription
0 The BOD33 Detection interrupt is disabled.
1 The BOD33 Detection interrupt is enabled, and an interrupt request will be generated when the BOD33 Detection Interrupt flag is set.

Bit 9 – BOD33RDY: BOD33 Ready Interrupt Enable

BOD33 Ready Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the BOD33 Ready Interrupt Enable bit, which disables the BOD33 Ready interrupt.

ValueDescription
0 The BOD33 Ready interrupt is disabled.
1 The BOD33 Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Ready Interrupt flag is set.

Bit 8 – DFLLRCS: DFLL Reference Clock Stopped Interrupt Enable

DFLL Reference Clock Stopped Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the DFLL Reference Clock Stopped Interrupt Enable bit, which disables the DFLL Reference Clock Stopped interrupt.

ValueDescription
0 The DFLL Reference Clock Stopped interrupt is disabled.
1 The DFLL Reference Clock Stopped interrupt is enabled, and an interrupt request will be generated when the DFLL Reference Clock Stopped Interrupt flag is set.

Bit 7 – DFLLLCKC: DFLL Lock Coarse Interrupt Enable

DFLL Lock Coarse Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the DFLL Lock Coarse Interrupt Enable bit, which disables the DFLL Lock Coarse interrupt.

ValueDescription
0 The DFLL Lock Coarse interrupt is disabled.
1 The DFLL Lock Coarse interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Coarse Interrupt flag is set.

Bit 6 – DFLLLCKF: DFLL Lock Fine Interrupt Enable

DFLL Lock Fine Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the DFLL Lock Fine Interrupt Enable bit, which disables the DFLL Lock Fine interrupt.

ValueDescription
0 The DFLL Lock Fine interrupt is disabled.
1 The DFLL Lock Fine interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Fine Interrupt flag is set.

Bit 5 – DFLLOOB: DFLL Out Of Bounds Interrupt Enable

DFLL Out Of Bounds Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the DFLL Out Of Bounds Interrupt Enable bit, which disables the DFLL Out Of Bounds interrupt.

ValueDescription
0 The DFLL Out Of Bounds interrupt is disabled.
1 The DFLL Out Of Bounds interrupt is enabled, and an interrupt request will be generated when the DFLL Out Of Bounds Interrupt flag is set.

Bit 4 – DFLLRDY: DFLL Ready Interrupt Enable

DFLL Ready Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the DFLL Ready Interrupt Enable bit, which disables the DFLL Ready interrupt.

ValueDescription
0 The DFLL Ready interrupt is disabled.
1 The DFLL Ready interrupt is enabled, and an interrupt request will be generated when the DFLL Ready Interrupt flag is set.

Bit 3 – OSC8MRDY: OSC8M Ready Interrupt Enable

OSC8M Ready Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the OSC8M Ready Interrupt Enable bit, which disables the OSC8M Ready interrupt.

ValueDescription
0 The OSC8M Ready interrupt is disabled.
1 The OSC8M Ready interrupt is enabled, and an interrupt request will be generated when the OSC8M Ready Interrupt flag is set.

Bit 2 – OSC32KRDY: OSC32K Ready Interrupt Enable

OSC32K Ready Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the OSC32K Ready Interrupt Enable bit, which disables the OSC32K Ready interrupt.

ValueDescription
0 The OSC32K Ready interrupt is disabled.
1 The OSC32K Ready interrupt is enabled, and an interrupt request will be generated when the OSC32K Ready Interrupt flag is set.

Bit 1 – XOSC32KRDY: XOSC32K Ready Interrupt Enable

XOSC32K Ready Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will set the XOSC32K Ready Interrupt Enable bit, which enables the XOSC32K Ready interrupt.

ValueDescription
0 The XOSC32K Ready interrupt is disabled.
1 The XOSC32K Ready interrupt is enabled, and an interrupt request will be generated when the XOSC32K Ready Interrupt flag is set.

Bit 0 – XOSCRDY: XOSC Ready Interrupt Enable

XOSC Ready Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will set the XOSC Ready Interrupt Enable bit, which enables the XOSC Ready interrupt.

ValueDescription
0 The XOSC Ready interrupt is disabled.
1 The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC Ready Interrupt flag is set.