APBBMASK

APBB Mask

  0x1C 32 Write-Protected 0x0000007F  
Parent topic: Register Description

APBB Mask

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
          PORT NVMCTRL DSU PAC1  
Access          R/W R/W R/W R/W  
Reset          1 1 1 1  

Bit 3 – PORT: PORT APB Clock Enable

PORT APB Clock Enable

ValueDescription
0 The APBB clock for the PORT is stopped.
1 The APBB clock for the PORT is enabled.

Bit 2 – NVMCTRL: NVMCTRL APB Clock Enable

NVMCTRL APB Clock Enable

ValueDescription
0 The APBB clock for the NVMCTRL is stopped.
1 The APBB clock for the NVMCTRL is enabled.

Bit 1 – DSU: DSU APB Clock Enable

DSU APB Clock Enable

ValueDescription
0 The APBB clock for the DSU is stopped.
1 The APBB clock for the DSU is enabled.

Bit 0 – PAC1: PAC1 APB Clock Enable

PAC1 APB Clock Enable

ValueDescription
0 The APBB clock for the PAC1 is stopped.
1 The APBB clock for the PAC1 is enabled.