Interrupt Enable Clear
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EVDn | EVDn | EVDn | EVDn | EVDn | EVDn | EVDn | EVDn | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OVRn | OVRn | OVRn | OVRn | OVRn | OVRn | OVRn | OVRn | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Channel n Event Detection Interrupt Enable [n=7..0]
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Event Detected Channel n Interrupt Enable bit, which disables the Event Detected Channel n interrupt.
| Value | Description |
|---|---|
| 0 | The Event Detected Channel n interrupt is disabled. |
| 1 | The Event Detected Channel n interrupt is enabled. |
Channel n Overrun Interrupt Enable [n=7..0]
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Channel n Interrupt Enable bit, which disables the Overrun Channel n interrupt.
| Value | Description |
|---|---|
| 0 | The Overrun Channel n interrupt is disabled. |
| 1 | The Overrun Channel n interrupt is enabled. |