The synchronization will delay write and
read accesses by a certain amount. This delay D is within the range of:
5×PGCLK+2×PAPB<D<6×PGCLK+3×PAPB
Where
PGCLK
is the period of the generic clock and
PAPB
is the period of the peripheral bus clock. A normal
peripheral bus register access duration is
2×PAPB
.