Interrupts

The ADC features three separate interrupt vectors. When one of the interrupt conditions occurs, an interrupt flag is set, and the CPU is notified and pointed to the corresponding Interrupt Service Routine (ISR). The following table shows the available interrupt vectors for the ADC.

Table 1. Available Interrupt Vectors and Sources
Name	Vector Description	Interrupt Flag	Conditions
ERROR	Error interrupt	TRIGOVR	A new conversion is triggered while one is ongoing
		SAMPOVR	A new conversion overwrites an unread sample in ADCn.SAMPLE
		RESOVR	A new conversion or accumulation overwrites an unread result in ADCn.RESULT
SAMPRDY	Sample Ready interrupt	SAMPRDY	The sample is available in ADCn.SAMPLE
SAMPRDY	Sample Ready interrupt	WCMP	As defined by WINSRC and WINCM in ADCn.CTRLD
RESRDY	Result Ready interrupt	RESRDY	The result is available in ADCn.RESULT
RESRDY	Result Ready interrupt	WCMP	As defined by WINSRC and WINCM in ADCn.CTRLD

An interrupt source is enabled or disabled by writing to the corresponding bit in the Interrupt Control (ADCn.INTCTRL) register as shown in the code snippet below.

ADC0.INTCTRL = ADC_RESRDY_bm; /* Enable Result Ready interrupt */

The interrupt flag is cleared by writing a '1' to the bit position in the Interrupt Flags (ADCn.INTFLAGS) register as shown in the code snippet below.

ADC0.INTFLAGS = ADC_RESRDY_bm; /* Clear Result Ready interrupt flag */

Interrupt flags SAMPRDY and RESRDY can also be cleared by reading respectively the ADCn.SAMPLE and ADCn.RESULT registers.