The ADC clock (CLK_ADC) is scaled down from the peripheral clock (CLK_PER). This can be configured by the Prescaler (PRESC) bit field in the CTRLB (ADCn.CTRLB) register.
ADC0.CTRLB = ADC_PRESC_DIV20_gc; /* CLK_ADC = CLK_PER/20 */
Some of the internal timings in the ADC and the PGA are independent of CLK_ADC. To ensure correct internal timing regardless of the ADC clock frequency, a 1 μs timebase (given in CLK_PER cycles) must be written to the TIMEBASE bit field in the Control C (ADCn.CTRLC) register. The timebase must be rounded up to the closest integer. The following code snippet shows how this can be done using the ceil function.
#include <math.h>
#define F_CPU 3333333ul
#define TIMEBASE_VALUE ((uint8_t) ceil(F_CPU*0.000001))
ADC0.CTRLC = (TIMEBASE_VALUE << ADC_TIMEBASE_gp);