PGA Bias and Output Sample Duration

The PGA Bias Select (PGABIASSEL) bit field in the ADC PGA Control (ADCn.PGACTRL) register can be configured to reduce the power consumption depending on the ADC clock frequency. The ADC PGA Sample Duration (ADCPGASAMPDUR) bit field can be configured to reduce the number of CLK_ADC cycles the ADC is sampling the output of the PGA. This is also dependent of the ADC clock frequency.

See the register description for these bit fields in the data sheet for recommended combinations of f_{CLK_ADC} and PGABIASSEL and ADCPGASAMPDUR.

An example configuration is shown below.

ADC0.PGACTRL = ADC_GAIN_16X_gc | /* 16x gain */
               ADC_PGABIASSEL_100PCT_gc | /* 100% bias current */
               ADC_ADCPGASAMPDUR_32CLK_gc | /* 32 cycles sampling of the PGA */
               ADC_PGAEN_bm; /* Enable the PGA */

Note: PGA Control is one of few AVR registers with a nonzero reset value. This must be taken into account if only configuring parts of the register.