SelfTest Command

The SelfTest command performs a test of one or more of the cryptographic engines within the ATECC608A-TNGTLS chip. Some or all of the algorithms will be tested depending on the Input mode parameter.

For the ATECC608A-TNGTLS device, the SelfTest command has been disabled from running automatically after a Power-up or Wake event. However, the command may be executed by the system if so desired. There is no requirement to run this test.

If any self test fails, whether called automatically on power-up, wake or via this command, the chip will enter a Failure state, in which chip operation is limited. The stored Failure state is always cleared upon a wake or power cycle. Note that the self-test failure (error code: 0x07) is not the same as a health-test failure (error code: 0x08).

When in the Failure state, the following operations are allowed:

Reads of the Configuration zone.
This self-test command. If a particular test is re-run and passes on the subsequent attempt, that bit in the Failure register will be cleared. If all bits are cleared, then ATECC608A-TNGTLS resumes normal command operation.
The current state of the Failure register can be read by calling this self-test command with a mode parameter of 0.
Any other command or reads of any other zone, will return an error code of 0x07. Use SelfTest(0) to determine the cause of the failure

Table 1. Input Parameters Self Test
Opcode (1 Byte)	Mode (1 Byte)¹							Param2 (2 Bytes)
Opcode (1 Byte)	b[7:6]	b[5]	b[4]	b[3]	b[2]	b[1]	b[0]	Param2 (2 Bytes)
	`2’b00`	SHA	AES	ECDH	ECDSA (Sign, Verify)	0	RNG, DRBG	0x00 00

Note:

1.Any combination of tests can be run at one time. Setting the corresponding mode bit to ‘1’ indicates that the test will be run. If the bit is ‘0’, then the test will not be run.

Table 2. Output Response Self Test
Name	Size	Description
Success	1 byte	0x00 - All Tests Passed Failure Map - one for each test that failed. Failure bits align with bits in Mode byte.