Contents

Introduction References Acronyms 4. Development Tools 4.1. PolarFire SoC MSS Configurator 4.1.1. Installation 4.1.2. Running the PolarFire SoC MSS Configurator 4.2. Libero® SoC 4.3. SoftConsole 4.3.1. SoftConsole Presets 4.3.1.1. Build Options 4.3.1.2. Debug Configurations 4.3.2. Debugging using SoftConsole 4.3.2.1. Launching a Debug Configuration 4.3.2.2. Perspectives 4.3.2.3. Debugging a Hart 4.3.2.4. Debug Session Controls 4.3.2.5. Setting Breakpoints 4.3.2.6. Setting Watchpoints 4.3.3. Renode™ 4.4. FlashPro Express 4.5. RISC-V GCC Bare Metal 4.6. RISC-V Linux Toolchain 4.7. Yocto 4.8. Buildroot 4.9. SmartDebug 4.10. Identify 5. Software Stack 5.1. RISC-V Libraries 5.1.1. Newlib 5.1.2. Binutils 5.2. Hart Software Services (HSS) 5.3. Bare Metal Library 5.4. Linker Scripts 5.5. Linux Images 5.6. FreeRTOS™ 5.7. Third Party Tools 6. Application Development 6.1. Device Boot and Configuration Process 6.2. Boot Mode 0-Idle Boot 6.3. Boot Mode 1-Direct Boot from eNVM 6.3.1. Programming the eNVM 6.4. Clock Management 6.5. Physical Memory Protection (PMP) 6.5.1. Using the PMPs in Bare Metal 6.5.2. Using the PMPs in Linux 6.6. Generating Boot Images 6.6.1. Targeting Harts 6.6.2. Storing a Single Bare Metal Application in an eNVM 6.6.3. Storing Bare Metal Application(s) to an External Memory 6.6.3.1. Single Bare Metal Application 6.6.3.2. Multiple Bare Metal Applications 6.6.4. Programming the eNVM 6.6.5. Unused Harts 6.7. Bare Metal Development 6.7.1. Single U54 6.7.2. Multiple U54s 6.7.3. Initializing the Application Execution Space (LIM or DDR) 6.7.4. Merging Multiple Bare Metal Applications 6.8. Linux Application Development 6.8.1. Building Linux Images 6.8.2. Integrating Linux Applications in Yocto 6.8.2.1. Existing Linux Applications 6.8.2.2. Custom Linux Applications 6.8.3. Integrating Linux Application in Buildroot 6.8.3.1. Existing Linux Applications 6.8.3.2. Custom Linux Applications 6.8.4. Different Sources of Booting 6.8.5. Device Tree Source (DTS) 6.8.5.1. Adding a Sample Device Node for GPIO 6.8.5.2. Adding a Sample Device node for LSRAM (UIO Framework) 7. Appendix 8. Revision History 9. Microchip FPGA Support The Microchip Website Product Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service