Contents

Introduction Features 1. Configuration Summary 2. Block Diagram 3. Signal Description 4. Microchip Recommended Power Management Solutions 4.1. MCP16502 PMIC 4.2. MCP16501 PMIC 5. Safety and Security Features 5.1. Design for Safety and IEC60730 Class B Certification 5.1.1. Background Information 5.2. Design for Security 5.3. Safety and IEC 60730 Features 5.4. Security Features 6. Package and Pinout 6.1. Packages 6.2. Pinout 7. Memories 7.1. Embedded Memories 7.1.1. Internal SRAM 7.1.2. Internal ROM 7.1.3. Boot Strategies 7.2. External Memory 7.2.1. External Bus Interface 7.2.2. Supported Memories on MPDDRC/SDRAMC Interface 7.2.3. Supported Memories on Static Memories and NAND Flash Interfaces 7.2.4. DDR/SDR I/O Calibration and DDR Voltage Reference 7.2.4.1. DDR/SDR I/O Calibration 7.2.4.2. DDR_VREF Recommended Circuits 8. System Controller 8.1. Power-On Reset 9. Peripherals 9.1. Peripheral Mapping 9.2. Peripheral Identifiers 9.3. FLEXCOM Features 9.4. Peripheral Signal Multiplexing on I/O Lines 10. ARM926EJ-S Processor 11. Debug and Test 11.1. Description 11.2. Embedded Characteristics 11.3. Block Diagram 11.4. Application Examples 11.4.1. Debug Environment 11.4.2. Test Environment 11.5. Debug and Test Pin Description 11.6. Functional Description 11.6.1. EmbeddedICE™ 11.6.2. JTAG Signal Description 11.6.3. Debug Unit 11.6.4. IEEE 1149.1 JTAG Boundary Scan 11.6.5. JTAG ID Code Register 12. Boot Strategies 12.1. Description 12.2. Flow Diagram 12.3. Chip Setup 12.4. Boot Configuration 12.4.1. Default Boot Sequence (Without Boot Configuration Packet) 12.4.2. Using Boot Configuration Packet 12.4.3. BSC_CR 12.4.4. Boot Configuration User Interface 12.4.4.1. MON_DIS 12.4.4.2. JTAG_DIS 12.4.4.3. CONSOLE_PIN 12.4.4.4. MEM_CFGx[0] 12.4.4.5. MEM_CFGx[1] 12.4.4.6. MEM_CFGx[0] 12.4.4.7. MEM_CFGx[1] 12.4.4.8. MEM_CFGx[0] 12.4.4.9. MEM_CFGx[1] 12.4.4.10. MEM_CFGx[0] 12.4.4.11. MEM_CFGx[1] 12.4.5. NVM Boot Sequence 12.4.6. Valid Code Detection 12.4.6.1. Arm Exception Vectors Check 12.4.6.2. boot.bin File Check 12.4.7. Detailed Memory Boot Procedures 12.4.7.1. NAND Flash Boot: NAND Flash Detection 12.4.7.1.1. Method 1 (recommended): NAND Flash Specific Header Detection 12.4.7.1.1.1. NAND Flash Specific Header Detection 12.4.7.2. NAND Flash Boot: PMECC Error Detection and Correction 12.4.7.3. SDCard/e.MMC Boot 12.4.7.4. SPI Flash Boot 12.4.7.5. QSPI NOR Flash Boot 12.4.8. Hardware and Software Constraints 12.5. SAM-BA Monitor 12.5.1. Command List 12.5.2. DBGU/UART Console Port 12.5.2.1. Xmodem Protocol 12.5.3. USB Device Port 12.5.3.1. Supported External Crystal / External Clocks 12.5.3.2. USB Class 12.5.3.3. Enumeration Process 12.5.3.4. Communication Endpoints 13. System Controller Write Protection (SYSCWP) 13.1. Functional Description 13.1.1. System Controller Peripheral Mapping 13.1.2. Register Write Protection 13.2. Register Summary 13.2.1. SYSC Write Protection Mode Register 13.2.2. SYSC Write Protection Status Register 14. General Purpose Backup Registers (GPBR) 14.1. Description 14.2. Embedded Characteristics 14.3. Register Summary 14.3.1. GPBR Mode Register 14.3.2. GPBR_FCLR 14.3.3. General Purpose Backup Register x [x=0..7] 15. Watchdog Timer (WDT) 15.1. Description 15.2. Embedded Characteristics 15.3. Block Diagram 15.4. Functional Description 15.5. Register Summary 15.5.1. Watchdog Timer Control Register 15.5.2. Watchdog Timer Mode Register 15.5.3. Watchdog Timer Value Register 15.5.4. Watchdog Timer Window Level Register 15.5.5. Watchdog Timer Interrupt Level Register 15.5.6. Watchdog Interrupt Enable Register 15.5.7. Watchdog Interrupt Disable Register 15.5.8. Watchdog Interrupt Status Register 15.5.9. Watchdog Interrupt Mask Register 16. Reset Controller (RSTC) 16.1. Description 16.2. Embedded Characteristics 16.3. Block Diagram 16.4. Functional Description 16.4.1. NRST Manager 16.4.1.1. NRST Signal or Interrupt 16.4.1.2. NRST_OUT External Reset Control 16.4.2. Reset States 16.4.2.1. General Reset 16.4.2.2. Backup Exit Reset 16.4.2.3. 32.768 kHz Crystal Oscillator Failure Detection Reset 16.4.2.4. Watchdog Reset 16.4.2.5. Software Reset 16.4.2.6. User Reset 16.4.3. Reset State Priorities 16.5. Register Summary 16.5.1. RSTC Control Register 16.5.2. RSTC Status Register 16.5.3. RSTC Mode Register 17. Real-time Timer (RTT) 17.1. Description 17.2. Embedded Characteristics 17.3. Block Diagram 17.4. Functional Description 17.5. Register Summary 17.5.1. Real-time Timer Mode Register 17.5.2. Real-time Timer Alarm Register 17.5.3. Real-time Timer Value Register 17.5.4. Real-time Timer Status Register 17.5.5. Real-time Timer Modulo Selection Register 17.5.6. RTT_TSR 18. Real-time Clock (RTC) 18.1. Description 18.2. Embedded Characteristics 18.3. Block Diagram 18.4. Product Dependencies 18.4.1. Power Management 18.4.2. Interrupt 18.5. Functional Description 18.5.1. Reference Clock 18.5.2. Timing 18.5.3. Alarm 18.5.4. Error Checking when Programming 18.5.5. RTC Internal Free-Running Counter Error Checking 18.5.6. Updating Time/Calendar 18.5.6.1. Gregorian and Persian Modes 18.5.6.2. UTC Mode 18.5.7. RTC Accurate Clock Calibration 18.5.8. Waveform Generation 18.5.9. Tamper Control Registers and Detection Logic 18.5.10. Tamper Timestamping 18.6. Register Summary 18.6.1. RTC Control Register 18.6.2. RTC Mode Register 18.6.3. RTC Time Register 18.6.4. RTC Time Register (UTC_MODE) 18.6.5. RTC Calendar Register 18.6.6. RTC Time Alarm Register 18.6.7. RTC Time Alarm Register (UTC_MODE) 18.6.8. RTC Calendar Alarm Register 18.6.9. RTC Calendar Alarm Register (UTC_MODE) 18.6.10. RTC Status Register 18.6.11. RTC Status Clear Command Register 18.6.12. RTC Interrupt Enable Register 18.6.13. RTC Interrupt Disable Register 18.6.14. RTC Interrupt Mask Register 18.6.15. RTC Valid Entry Register 18.6.16. RTC TimeStamp Time Register 0 18.6.17. RTC TimeStamp Time Register 0 (UTC_MODE) 18.6.18. RTC TimeStamp Time Register 1 18.6.19. RTC TimeStamp Time Register 1 (UTC_MODE) 18.6.20. RTC TimeStamp Date Register 18.6.21. RTC TimeStamp Date Register (UTC_MODE) 18.6.22. RTC TimeStamp Source Register 18.6.23. RTC_TMR 18.6.24. RTC_TDPR 19. Shutdown Controller (SHDWC) 19.1. Description 19.2. Embedded Characteristics 19.3. Block Diagram 19.4. I/O Lines Description 19.5. Product Dependencies 19.5.1. Power Management 19.6. Functional Description 19.6.1. Wake-up Inputs 19.7. Register Summary 19.7.1. SHDWC Control Register 19.7.2. SHDWC Mode Register 19.7.3. SHDWC Status Register 19.7.4. SHDWC Wake-up Inputs Register 20. Periodic Interval Timer (PIT) 20.1. Description 20.2. Embedded Characteristics 20.3. Block Diagram 20.4. Functional Description 20.5. Register Summary 20.5.1. Periodic Interval Timer Mode Register 20.5.2. Periodic Interval Timer Status Register 20.5.3. Periodic Interval Timer Value Register 20.5.4. Periodic Interval Timer Image Register 21. 64-bit Periodic Interval Timer (PIT64B) 21.1. Description 21.2. Embedded Characteristics 21.3. Block Diagram 21.4. Product Dependencies 21.4.1. Power Management 21.4.2. Interrupt Generation 21.5. Functional Description 21.5.1. Timer Clock Source 21.5.2. Single Period Mode 21.5.3. Continuous Period Mode 21.5.4. Security and Safety Analysis and Reports 21.5.5. Register Write Protection 21.6. Register Summary 21.6.1. PIT64B Control Register 21.6.2. PIT64B Mode Register 21.6.3. PIT64B LSB Period Register 21.6.4. PIT64B MSB Period Register 21.6.5. PIT64B Interrupt Enable Register 21.6.6. PIT64B Interrupt Disable Register 21.6.7. PIT64B Interrupt Mask Register 21.6.8. PIT64B Interrupt Status Register 21.6.9. PIT64B Timer LSB Register 21.6.10. PIT64B Timer MSB Register 21.6.11. PIT64B Write Protection Mode Register 21.6.12. PIT64B Write Protection Status Register 22. Debug Unit (DBGU) 22.1. Description 22.2. Embedded Characteristics 22.3. Block Diagram 22.4. Product Dependencies 22.4.1. I/O Lines 22.4.2. Power Management 22.4.3. Interrupt Sources 22.5. Functional Description 22.5.1. Baud Rate Generator 22.5.2. Receiver 22.5.2.1. Receiver Reset, Enable and Disable 22.5.2.2. Start Detection and Data Sampling 22.5.2.3. Receiver Ready 22.5.2.4. Receiver Overrun 22.5.2.5. Parity Error 22.5.2.6. Receiver Framing Error 22.5.2.7. Receiver Digital Filter 22.5.2.8. Receiver Timeout 22.5.3. Transmitter 22.5.3.1. Transmitter Reset, Enable and Disable 22.5.3.2. Transmit Format 22.5.3.3. Transmitter Control 22.5.4. DMA Support 22.5.5. Register Write Protection 22.5.6. Test Modes 22.5.7. Debug Communication Channel Support 22.5.8. Chip Identifier 22.5.9. ICE Access Prevention 22.6. Register Summary 22.6.1. DBGU Control Register 22.6.2. DBGU Mode Register 22.6.3. DBGU Interrupt Enable Register 22.6.4. DBGU Interrupt Disable Register 22.6.5. DBGU Interrupt Mask Register 22.6.6. DBGU Status Register 22.6.7. DBGU Receiver Holding Register 22.6.8. DBGU Transmit Holding Register 22.6.9. DBGU Baud Rate Generator Register 22.6.10. DBGU Receiver Timeout Register 22.6.11. DBGU_CIDR 22.6.12. DBGU Chip ID Extension Register 22.6.13. Debug Unit Force NTRST Register 22.6.14. DBGU Write Protection Mode Register 23. OTP Memory Controller (OTPC) 23.1. Description 23.2. Embedded Characteristics 23.3. Block Diagram 23.4. Functional Description 23.4.1. Bus Interfaces 23.4.2. OTP Memory Partitioning 23.4.3. User Area 23.4.3.1. Area Configuration and Control 23.4.3.2. Area Mapping 23.4.3.3. Packet Definition 23.4.3.3.1. Header Field 23.4.3.3.2. “Special” Packets 23.4.3.4. Init 23.4.3.5. Read Access 23.4.3.5.1. Transfer a Packet through the Master Key Bus 23.4.3.5.2. Hiding a Packet 23.4.3.6. Write (Program) Considerations 23.4.3.6.1. ‘1’ in the Header 23.4.3.6.2. ‘1’ in the Payload 23.4.3.7. Write (Program) Access 23.4.3.7.1. Writing a New Packet from the User Interface 23.4.3.7.2. Updating an Existing Packet from the User Interface 23.4.3.7.3. Writing a Packet from the Slave Key Bus 23.4.3.7.4. Locking a Packet 23.4.3.7.5. Invalidating a Packet 23.4.3.8. Fixing Corruption 23.4.3.9. “Software” Protections 23.4.3.10. “Hardware” Protections 23.4.4. OTP Emulation Mode 23.4.5. Interrupts 23.4.6. Register Write Protection 23.5. Register Summary 23.5.1. OTPC Control Register 23.5.2. OTPC Mode Register 23.5.3. OTPC Address Register 23.5.4. OTPC Status Register 23.5.5. OTPC Interrupt Enable Register 23.5.6. OTPC Interrupt Disable Register 23.5.7. OTPC Interrupt Mask Register 23.5.8. OTPC Interrupt Status Register 23.5.9. OTPC Header Register 23.5.10. OTPC Data Register 23.5.11. OTPC Boot Addresses Register 23.5.12. OTPC Custom Address Register 23.5.13. OTPC User Hardware Configuration 0 Register 23.5.14. OTPC User Hardware Configuration 1 Register 23.5.15. OTPC Product UID x Register 23.5.16. OTPC Write Protection Mode Register 23.5.17. OTPC Write Protection Status Register 24. Special Function Registers (SFR) 24.1. Description 24.2. Embedded Characteristics 24.3. Register Summary 24.3.1. EBI Chip Select Register 24.3.2. OHCI Interrupt Configuration Register 24.3.3. OHCI Interrupt Status Register 24.3.4. UTMI High-Speed Trimming Register 24.3.5. UTMI Full-Speed Trimming Register 24.3.6. UTMI DP/DM Pin Swapping Register 24.3.7. SFR Light Sleep Register 24.3.8. SFR Write Protection Mode Register 25. Bus Matrix (MATRIX) 25.1. Description 25.1.1. MATRIX Masters 25.1.2. MATRIX Slaves 25.1.3. Master to Slave Access 25.2. Embedded Characteristics 25.3. Memory Mapping 25.4. Special Bus Granting Techniques 25.5. No Default Master 25.6. Last Access Master 25.7. Fixed Default Master 25.8. Arbitration 25.8.1. Arbitration Scheduling 25.8.1.1. Undefined Length Burst Arbitration 25.8.1.2. Slot Cycle Limit Arbitration 25.8.2. Arbitration Priority Scheme 25.8.2.1. Fixed Priority Arbitration 25.8.2.2. Round-Robin Arbitration 25.9. Register Write Protection 25.10. Register Summary 25.10.1. MATRIX Master Configuration Register x 25.10.2. MATRIX Slave Configuration Register x 25.10.3. MATRIX Priority Register A For Slaves x 25.10.4. MATRIX Priority Register B For Slaves x 25.10.5. MATRIX Master Remap Control Register 25.10.6. MATRIX Master Error Interrupt Enable Register 25.10.7. MATRIX Master Error Interrupt Disable Register 25.10.8. MATRIX Master Error Interrupt Mask Register 25.10.9. MATRIX Master Error Status Register 25.10.10. MATRIX Master Error Address Register x 25.10.11. MATRIX Write Protection Mode Register 25.10.12. MATRIX Write Protection Status Register 26. Advanced Interrupt Controller (AIC) 26.1. Description 26.2. Embedded Characteristics 26.3. Block Diagram 26.4. Application Block Diagram 26.5. AIC Detailed Block Diagram 26.6. I/O Line Description 26.7. Product Dependencies 26.7.1. I/O Lines 26.7.2. Power Management 26.7.3. Interrupt Sources 26.8. Functional Description 26.8.1. Interrupt Source Control 26.8.1.1. Interrupt Source Mode 26.8.1.2. Interrupt Source Enabling 26.8.1.3. Interrupt Clearing and Setting 26.8.1.4. Interrupt Status 26.8.1.5. Internal Interrupt Source Input Stage 26.8.1.6. External Interrupt Source Input Stage 26.8.2. Interrupt Latencies 26.8.2.1. External Interrupt Edge Triggered Source 26.8.2.2. External Interrupt Level Sensitive Source 26.8.2.3. Internal Interrupt Edge Triggered Source 26.8.2.4. Internal Interrupt Level Sensitive Source 26.8.3. Normal Interrupt 26.8.3.1. Priority Controller 26.8.3.2. Interrupt Nesting 26.8.3.3. Interrupt Vectoring 26.8.3.4. Interrupt Handlers 26.8.4. Fast Interrupt 26.8.4.1. Fast Interrupt Source 26.8.4.2. Fast Interrupt Control 26.8.4.3. Fast Interrupt Vectoring 26.8.4.4. Fast Interrupt Handlers 26.8.4.5. Fast Forcing 26.8.5. Protect Mode 26.8.6. Spurious Interrupt 26.8.7. General Interrupt Mask 26.8.8. Register Write Protection 26.9. Register Summary 26.9.1. AIC Source Select Register 26.9.2. AIC Source Mode Register 26.9.3. AIC Source Vector Register 26.9.4. AIC Interrupt Vector Register 26.9.5. AIC FIQ Vector Register 26.9.6. AIC Interrupt Status Register 26.9.7. AIC Interrupt Pending Register 0 26.9.8. AIC Interrupt Pending Register 1 26.9.9. AIC Interrupt Pending Register 2 26.9.10. AIC Interrupt Pending Register 3 26.9.11. AIC Interrupt Mask Register 26.9.12. AIC Core Interrupt Status Register 26.9.13. AIC End of Interrupt Command Register 26.9.14. AIC Spurious Interrupt Vector Register 26.9.15. AIC Interrupt Enable Command Register 26.9.16. AIC Interrupt Disable Command Register 26.9.17. AIC Interrupt Clear Command Register 26.9.18. AIC Interrupt Set Command Register 26.9.19. AIC Fast Forcing Enable Register 26.9.20. AIC Fast Forcing Disable Register 26.9.21. AIC Fast Forcing Status Register 26.9.22. AIC SVR Return Enable Register 26.9.23. AIC SVR Return Disable Register 26.9.24. AIC SVR Return Status Register 26.9.25. AIC Debug Control Register 26.9.26. AIC Write Protection Mode Register 26.9.27. AIC Write Protection Status Register 27. Slow Clock Controller (SCKC) 27.1. Description 27.2. Embedded Characteristics 27.3. Block Diagram 27.4. Functional Description 27.4.1. Switching from Embedded 32 kHz RC Oscillator to 32.768 kHz Crystal Oscillator 27.4.2. Bypassing the 32.768 kHz Crystal Oscillator 27.4.3. Switching from 32.768 kHz Crystal Oscillator to Embedded 32 kHz RC Oscillator 27.5. Register Summary 27.5.1. Slow Clock Controller Configuration Register 28. Clock Generator 28.1. Description 28.2. Embedded Characteristics 28.3. Block Diagram 28.4. Slow Clock 28.4.1. Slow RC Oscillator (32 kHz typical) 28.4.2. 32.768 kHz Crystal Oscillator 28.5. Main Clock 28.5.1. Main RC Oscillator 28.5.2. Main Crystal Oscillator 28.5.3. Main Clock Source Selection 28.5.4. Bypassing the Main Crystal Oscillator 28.5.5. Main Frequency Counter 28.6. PLL Controls 28.6.1. Divider and Phase Lock Loop Programming 28.6.2. PLL Unlock 28.6.3. Spread Spectrum 29. Power Management Controller (PMC) 29.1. Description 29.2. Embedded Characteristics 29.3. Block Diagram 29.4. Processor Clock Controller 29.5. USB Clock Controller 29.6. Free-running Processor Clock 29.7. Peripheral and Generic Clock Controller 29.8. Programmable Clock Output Controller 29.9. Ultra-Low Power Mode and Fast Startup 29.9.1. ULP Mode 1 29.9.2. Fast Startup 29.10. Main Crystal Oscillator Failure Detection 29.11. 32.768 kHz Crystal Oscillator Frequency Monitor 29.12. MCK Frequency Monitor 29.13. Recommended Programming Sequence 29.14. Clock Switching Details 29.14.1. CPU Clock Switching Timings 29.15. Register Write Protection 29.16. Register Summary 29.16.1. PMC System Clock Enable Register 29.16.2. PMC System Clock Disable Register 29.16.3. PMC System Clock Status Register 29.16.4. PMC PLL Control Register 0 29.16.5. PMC PLL Control Register 1 29.16.6. PMC PLL Spread Spectrum Register 29.16.7. PMC PLL Analog Control Register 29.16.8. PMC PLL Update Register 29.16.9. PMC Clock Generator Main Oscillator Register 29.16.10. PMC Clock Generator Main Clock Frequency Register 29.16.11. PMC CPU Clock Register 29.16.12. PMC USB Clock Register 29.16.13. PMC Programmable Clock Register 29.16.14. PMC Interrupt Enable Register 29.16.15. PMC Interrupt Disable Register 29.16.16. PMC Status Register 29.16.17. PMC Interrupt Mask Register 29.16.18. PMC Fast Startup Mode Register 29.16.19. PMC Wakeup Control Register 29.16.20. PMC Fault Output Clear Register 29.16.21. PMC Write Protection Mode Register 29.16.22. PMC Write Protection Status Register 29.16.23. PMC Peripheral Control Register 29.16.24. PMC MCK Monitor Limits Register 29.16.25. PMC Peripheral Clock Status Register 0 29.16.26. PMC Peripheral Clock Status Register 1 29.16.27. PMC Generic Clock Status Register 0 29.16.28. PMC Generic Clock Status Register 1 29.16.29. PMC PLL Interrupt Enable Register 29.16.30. PMC PLL Interrupt Disable Register 29.16.31. PMC PLL Interrupt Mask Register 29.16.32. PMC PLL Interrupt Status Register 0 29.16.33. PMC PLL Interrupt Status Register 1 30. Parallel Input/Output Controller (PIO) 30.1. Description 30.2. Embedded Characteristics 30.3. Block Diagram 30.4. Product Dependencies 30.4.1. Pin Multiplexing 30.4.2. External Interrupt Lines 30.4.3. Power Management 30.4.4. Interrupt Sources 30.5. Functional Description 30.5.1. Pullup and Pulldown Resistor Control 30.5.2. I/O Line or Peripheral Function Selection 30.5.3. Peripheral A or B or C or D Selection 30.5.4. Output Control 30.5.5. Synchronous Data Output 30.5.6. Multi-Drive Control (Open Drain) 30.5.7. Output Line Timings 30.5.8. Inputs 30.5.9. Input Glitch and Debouncing Filters 30.5.10. Input Edge/Level Interrupt 30.5.11. Programmable Schmitt Trigger 30.5.12. I/O Lines Programming Example 30.5.13. Register Write Protection 30.6. Register Summary 30.6.1. PIO Enable Register 30.6.2. PIO Disable Register 30.6.3. PIO Status Register 30.6.4. PIO Output Enable Register 30.6.5. PIO Output Disable Register 30.6.6. PIO Output Status Register 30.6.7. PIO Input Filter Enable Register 30.6.8. PIO Input Filter Disable Register 30.6.9. PIO Input Filter Status Register 30.6.10. PIO Set Output Data Register 30.6.11. PIO Clear Output Data Register 30.6.12. PIO Output Data Status Register 30.6.13. PIO Pin Data Status Register 30.6.14. PIO Interrupt Enable Register 30.6.15. PIO Interrupt Disable Register 30.6.16. PIO Interrupt Mask Register 30.6.17. PIO Interrupt Status Register 30.6.18. PIO Multi-driver Enable Register 30.6.19. PIO Multi-driver Disable Register 30.6.20. PIO Multi-driver Status Register 30.6.21. PIO Pull-Up Disable Register 30.6.22. PIO Pull-Up Enable Register 30.6.23. PIO Pull-Up Status Register 30.6.24. PIO Peripheral ABCD Select Register 1 30.6.25. PIO Peripheral ABCD Select Register 2 30.6.26. PIO Input Filter Slow Clock Disable Register 30.6.27. PIO Input Filter Slow Clock Enable Register 30.6.28. PIO Input Filter Slow Clock Status Register 30.6.29. PIO Slow Clock Divider Debouncing Register 30.6.30. PIO Pad Pull-Down Disable Register 30.6.31. PIO Pad Pull-Down Enable Register 30.6.32. PIO Pad Pull-Down Status Register 30.6.33. PIO Output Write Enable Register 30.6.34. PIO Output Write Disable Register 30.6.35. PIO Output Write Status Register 30.6.36. PIO Additional Interrupt Modes Enable Register 30.6.37. PIO Additional Interrupt Modes Disable Register 30.6.38. PIO Additional Interrupt Modes Mask Register 30.6.39. PIO Edge Select Register 30.6.40. PIO Level Select Register 30.6.41. PIO Edge/Level Status Register 30.6.42. PIO Falling Edge/Low-Level Select Register 30.6.43. PIO Rising Edge/High-Level Select Register 30.6.44. PIO Fall/Rise - Low/High Status Register 30.6.45. PIO Write Protection Mode Register 30.6.46. PIO Write Protection Status Register 30.6.47. PIO Schmitt Trigger Register 30.6.48. PIO_SLEWR 30.6.49. PIO I/O Drive Register 1 31. External Bus Interface (EBI) 31.1. Description 31.2. Embedded Characteristics 31.3. EBI Block Diagram 31.4. I/O Lines Description 31.5. Application Examples 31.5.1. Hardware Interface 31.5.2. Product Dependencies 31.5.2.1. I/O Lines 31.5.3. Functional Description 31.5.3.1. Bus Multiplexing 31.5.3.2. Pull-up and Pull-down Control 31.5.3.3. Voltage Level Control 31.5.3.4. Power Supplies 31.5.3.5. Static Memory Controller 31.5.3.6. Multi-Port DDR and SDRAM Controllers 31.5.3.7. Programmable Multibit ECC Controller 31.5.3.8. NAND Flash Support 31.5.4. Implementation Examples 31.5.4.1. 2x8-bit DDR2 on EBI 31.5.4.1.1. Hardware Configuration 31.5.4.1.2. Software Configuration 31.5.4.2. 16-bit LPDDR on EBI 31.5.4.2.1. Hardware Configuration 31.5.4.2.2. Software Configuration 31.5.4.3. 16-bit SDRAM on EBI 31.5.4.3.1. Hardware Configuration 31.5.4.3.2. Software Configuration 31.5.4.4. 2x16-bit SDRAM on EBI 31.5.4.4.1. Hardware Configuration 31.5.4.4.2. Software Configuration 31.5.4.5. 8-bit NAND Flash with NFD0_ON_D16 = 0 31.5.4.5.1. Hardware Configuration 31.5.4.5.2. Software Configuration 31.5.4.6. 8-bit NAND Flash with NFD0_ON_D16 = 1 31.5.4.6.1. Hardware Configuration 31.5.4.6.2. Software Configuration 31.5.4.7. NOR Flash on NCS0 31.5.4.7.1. Hardware Configuration 31.5.4.7.2. Software Configuration 32. AHB Multiport DDR-SDRAM Controller (MPDDRC) 32.1. Description 32.2. Embedded Characteristics 32.3. Block Diagram 32.4. Product Dependencies, Initialization Sequence 32.4.1. Low-power DDR1-SDRAM Initialization 32.4.2. DDR2-SDRAM Initialization 32.5. Functional Description 32.5.1. DDR-SDRAM Controller Write Cycle 32.5.2. DDR-SDRAM Controller Read Cycle 32.5.3. Refresh (Autorefresh Command) 32.5.4. Power Management 32.5.4.1. Self-refresh Mode 32.5.4.2. Powerdown Mode 32.5.4.3. Deep Powerdown Mode 32.5.4.4. Change Frequency During Self-Refresh Mode with Low-power DDR-SDRAM Devices 32.5.4.5. Reset Mode 32.5.5. Multiport Functionality 32.5.5.1. Round-robin Arbitration 32.5.5.2. Request-word Weighted Round-robin Arbitration 32.5.5.3. Bandwidth Weighted Round-robin Arbitration 32.5.5.4. Quality Of Service Arbitration 32.5.6. Scrambling/Unscrambling Function 32.5.7. Clearing Scrambling Keys on Tamper Event 32.5.8. Register Write Protection 32.5.9. Monitor 32.5.10. Security and Safety Analysis and Reports 32.6. Software Interface/SDRAM Organization, Address Mapping 32.6.1. DDR-SDRAM Address Mapping for 16-bit Memory Data Bus Width 32.6.2. DDR-SDRAM Address Mapping for Low-cost Memories 32.7. Register Summary 32.7.1. MPDDRC Mode Register 32.7.2. MPDDRC Refresh Timer Register 32.7.3. MPDDRC Configuration Register 32.7.4. MPDDRC Timing Parameter 0 Register 32.7.5. MPDDRC Timing Parameter 1 Register 32.7.6. MPDDRC Timing Parameter 2 Register 32.7.7. MPDDRC Low-Power Register 32.7.8. MPDDRC Memory Device Register 32.7.9. MPDDRC I/O Calibration Register 32.7.10. MPDDRC OCMS Register 32.7.11. MPDDRC OCMS KEY1 Register 32.7.12. MPDDRC OCMS KEY2 Register 32.7.13. MPDDRC Configuration Arbiter Register 32.7.14. MPDDRC Timeout Register 32.7.15. MPDDRC Request Port 0-1-2-3 Register 32.7.16. MPDDRC Current/Maximum Bandwidth Port 0-1-2-3 Register 32.7.17. MPDDRC Read Data Path Register 32.7.18. MPDDRC Monitor Configuration Register 32.7.19. MPDDRC Monitor Address High/Low Port x Register 32.7.20. MPDDRC_MINFOx (MAX_WAIT) 32.7.21. MPDDRC_MINFOx (NB_TRANSFERS) 32.7.22. MPDDRC_MINFOx (TOTAL_LATENCY) 32.7.23. MPDDRC_MINFOx (TOTAL_LATENCY_QOS01) 32.7.24. MPDDRC_MINFOx (TOTAL_LATENCY_QOS23) 32.7.25. MPDDRC Interrupt Enable Register 32.7.26. MPDDRC Interrupt Disable Register 32.7.27. MPDDRC Interrupt Mask Register 32.7.28. MPDDRC Interrupt Status Register 32.7.29. MPDDRC Safety Register 32.7.30. MPDDRC Write Protection Mode Register 32.7.31. MPDDRC Write Protection Status Register 33. SDRAM Controller (SDRAMC) 33.1. Description 33.2. Embedded Characteristics 33.3. Signal Description 33.4. Software Interface/SDRAM Organization, Address Mapping 33.4.1. SDRAM Address Mapping for 32-bit Memory Data Bus Width 33.4.2. SDRAM Address Mapping for 16-bit Memory Data Bus Width 33.5. Product Dependencies 33.5.1. SDRAM Device Initialization 33.5.2. I/O Lines 33.5.3. Power Management 33.5.4. Interrupt Sources 33.6. Functional Description 33.6.1. SDRAM Controller Write Cycle 33.6.2. SDRAM Controller Read Cycle 33.6.3. Border Management 33.6.4. SDRAM Controller Refresh Cycles 33.6.5. Power Management 33.6.5.1. Self-refresh Mode 33.6.5.2. Low-power Mode 33.6.5.3. Deep Powerdown Mode 33.6.6. Scrambling/Unscrambling Function 33.6.7. Clearing Scrambling Keys on Tamper Event 33.6.8. Interface with Multiplexed Data/Address Lines and Data/Address/Command Lines 33.6.9. Register Write Protection 33.6.10. Security and Safety Analysis and Reports 33.7. Register Summary 33.7.1. SDRAMC Mode Register 33.7.2. SDRAMC Refresh Timer Register 33.7.3. SDRAMC Configuration Register 33.7.4. SDRAMC Low-Power Register 33.7.5. SDRAMC Interrupt Enable Register 33.7.6. SDRAMC Interrupt Disable Register 33.7.7. SDRAMC Interrupt Mask Register 33.7.8. SDRAMC Interrupt Status Register 33.7.9. SDRAMC Memory Device Register 33.7.10. SDRAMC Configuration Register 1 33.7.11. SDRAMC OCMS Register 33.7.12. SDRAMC OCMS KEY1 Register 33.7.13. SDRAMC OCMS KEY2 Register 33.7.14. SDRAMC Write Protection Mode Register 33.7.15. SDRAMC Write Protection Status Register 34. Static Memory Controller (SMC) 34.1. Description 34.2. Embedded Characteristics 34.3. I/O Lines Description 34.4. Interrupt Source 34.5. Multiplexed Signals 34.6. Application Example 34.6.1. Hardware Interface 34.7. Product Dependencies 34.7.1. I/O Lines 34.8. External Memory Mapping 34.9. Connection to External Devices 34.9.1. Data Bus Width 34.9.2. Byte Write or Byte Select Access 34.9.2.1. Byte Write Access 34.9.2.2. Byte Select Access 34.9.2.3. Signal Multiplexing 34.10. Standard Read and Write Protocols 34.10.1. Read Waveforms 34.10.1.1. NRD Waveform 34.10.1.2. NCS Waveform 34.10.1.3. Read Cycle 34.10.1.4. Null Delay Setup and Hold 34.10.1.5. Null Pulse 34.10.2. Read Mode 34.10.2.1. Read is Controlled by NRD (READ_MODE = 1) 34.10.2.2. Read is Controlled by NCS (READ_MODE = 0) 34.10.3. Write Waveforms 34.10.3.1. NWE Waveforms 34.10.3.2. NCS Waveforms 34.10.3.3. Write Cycle 34.10.3.4. Null Delay Setup and Hold 34.10.3.5. Null Pulse 34.10.4. Write Mode 34.10.4.1. Write is Controlled by NWE (WRITE_MODE = 1) 34.10.4.2. Write is Controlled by NCS (WRITE_MODE = 0) 34.10.5. Coding Timing Parameters 34.10.6. Reset Values of Timing Parameters 34.10.7. Usage Restriction 34.11. Automatic Wait States 34.11.1. Chip Select Wait States 34.11.2. Early Read Wait State 34.11.3. Reload User Configuration Wait State 34.11.3.1. User Procedure 34.11.3.2. Slow Clock Mode Transition 34.11.4. Read to Write Wait State 34.12. Data Float Wait States 34.12.1. READ_MODE 34.12.2. TDF Optimization Enabled (TDF_MODE = 1) 34.12.3. TDF Optimization Disabled (TDF_MODE = 0) 34.13. External Wait 34.13.1. Restriction 34.13.2. Frozen Mode 34.13.3. Ready Mode 34.13.4. NWAIT Latency and Read/Write Timings 34.14. Slow Clock Mode 34.15. Asynchronous Page Mode 34.15.1. Protocol and Timings in Page Mode 34.15.2. Byte Access Type in Page Mode 34.15.3. Page Mode Restriction 34.15.4. Sequential and Non-sequential Accesses 34.16. Register Write Protection 34.17. Security and Safety Analysis and Reports 34.18. Scrambling/Unscrambling Function 34.19. Clearing Scrambling Keys on a Tamper Event 34.20. Register Summary 34.20.1. SMC Setup Register 34.20.2. SMC Pulse Register 34.20.3. SMC Cycle Register 34.20.4. SMC Mode Register 34.20.5. SMC_OCMS 34.20.6. SMC_KEY1 34.20.7. SMC_KEY2 34.20.8. SMC_SRIER 34.20.9. SMC Write Protection Mode Register 34.20.10. SMC Write Protection Status Register 35. Programmable Multibit Error Correction Code Controller (PMECC) 35.1. Description 35.2. Embedded Characteristics 35.3. Block Diagram 35.4. Functional Description 35.4.1. MLC/SLC Write Page Operation using PMECC 35.4.1.1. SLC/MLC Write Operation with Spare Enable Bit Set 35.4.1.2. MLC/SLC Write Operation with Spare Area Disabled 35.4.2. MLC/SLC Read Page Operation using PMECC 35.4.2.1. MLC/SLC Read Operation with Spare Decoding 35.4.2.2. MLC/SLC Read Operation 35.4.2.3. MLC/SLC User Read ECC Area 35.5. Software Implementation 35.5.1. Remainder Substitution Procedure 35.5.2. Find the Error Location Polynomial Sigma(x) 35.5.3. Find the Error Position 35.6. Register Summary 35.6.1. PMECC Configuration Register 35.6.2. PMECC Spare Area Size Register 35.6.3. PMECC Start Address Register 35.6.4. PMECC End Address Register 35.6.5. PMECC Clock Control Register 35.6.6. PMECC Control Register 35.6.7. PMECC Status Register 35.6.8. PMECC Interrupt Enable Register 35.6.9. PMECC Interrupt Disable Register 35.6.10. PMECC Interrupt Mask Register 35.6.11. PMECC Interrupt Status Register 35.6.12. PMECC_ECCx 35.6.13. PMECC Remainder x Register 36. Programmable Multibit ECC Error Location Controller (PMERRLOC) 36.1. Description 36.2. Embedded Characteristics 36.3. Block Diagram 36.4. Functional Description 36.5. Register Summary 36.5.1. PMERRLOC Configuration Register 36.5.2. PMERRLOC Primitive Register 36.5.3. PMERRLOC Enable Register 36.5.4. PMERRLOC Disable Register 36.5.5. PMERRLOC Status Register 36.5.6. PMERRLOC Interrupt Enable Register 36.5.7. PMERRLOC Interrupt Disable Register 36.5.8. PMERRLOC Interrupt Mask Register 36.5.9. PMERRLOC Interrupt Status Register 36.5.10. PMERRLOC SIGMA0 Register 36.5.11. PMERRLOC SIGMAx Register 36.5.12. PMERRLOC Error Location x Register 37. DMA Controller (XDMAC) 37.1. Description 37.2. Embedded Characteristics 37.3. Block Diagram 37.4. DMA Controller Peripheral Connections 37.5. Functional Description 37.5.1. Basic Definitions 37.5.2. Data Striding Diagram 37.5.3. Transfer Hierarchy Diagrams 37.5.4. Peripheral Synchronized Transfer 37.5.4.1. Peripheral to Memory Transfer 37.5.4.2. Memory to Peripheral Transfer 37.5.4.3. Software Triggered Synchronized Transfer 37.5.5. XDMAC Transfer Software Operation 37.5.5.1. Single Block Transfer With Single Microblock 37.5.5.2. Single Block Transfer With Multiple Microblock 37.5.5.3. Master Transfer 37.5.5.4. Disabling A Channel Before Transfer Completion 37.6. Linked List Descriptor Operation 37.6.1. Linked List Descriptor View 37.6.1.1. Channel Next Descriptor View 0–3 Structures 37.6.2. Descriptor Structure Members Description 37.6.2.1. MBR_UBC 37.7. XDMAC Maintenance Software Operations 37.7.1. Disabling a Channel 37.7.2. Suspending a Channel 37.7.3. Flushing a Channel 37.7.4. Maintenance Operation Priority 37.7.4.1. Disable Operation Priority 37.7.4.2. Flush Operation Priority 37.7.4.3. Suspend Operation Priority 37.8. XDMAC Software Requirements 37.9. Register Summary 37.9.1. XDMAC_GTYPE 37.9.2. XDMAC Global Configuration Register 37.9.3. XDMAC Global Weighted Arbiter Configuration Register 37.9.4. XDMAC Global Interrupt Enable Register 37.9.5. XDMAC Global Interrupt Disable Register 37.9.6. XDMAC Global Interrupt Mask Register 37.9.7. XDMAC Global Interrupt Status Register 37.9.8. XDMAC Global Channel Enable Register 37.9.9. XDMAC Global Channel Disable Register 37.9.10. XDMAC Global Channel Status Register 37.9.11. XDMAC Global Channel Read Suspend Register 37.9.12. XDMAC Global Channel Write Suspend Register 37.9.13. XDMAC Global Channel Read Write Suspend Register 37.9.14. XDMAC Global Channel Read Write Resume Register 37.9.15. XDMAC Global Channel Software Request Register 37.9.16. XDMAC Global Channel Software Request Status Register 37.9.17. XDMAC Global Channel Software Flush Request Register 37.9.18. XDMAC Channel x Interrupt Enable Register [x=0..15] 37.9.19. XDMAC Channel x Interrupt Disable Register [x = 0..15] 37.9.20. XDMAC Channel x Interrupt Mask Register [x = 0..15] 37.9.21. XDMAC Channel x Interrupt Status Register [x = 0..15] 37.9.22. XDMAC Channel x Source Address Register [x = 0..15] 37.9.23. XDMAC Channel x Destination Address Register [x = 0..15] 37.9.24. XDMAC Channel x Next Descriptor Address Register [x = 0..15] 37.9.25. XDMAC Channel x Next Descriptor Control Register [x = 0..15] 37.9.26. XDMAC Channel x Microblock Control Register [x = 0..15] 37.9.27. XDMAC Channel x Block Control Register [x = 0..15] 37.9.28. XDMAC Channel x Configuration Register [x = 0..15] 37.9.29. XDMAC Channel x Data Stride Memory Set Pattern Register [x = 0..15] 37.9.30. XDMAC Channel x Source Microblock Stride Register [x = 0..15] 37.9.31. XDMAC Channel x Destination Microblock Stride Register [x = 0..15] 38. LCD Controller (LCDC) 38.1. Description 38.2. Embedded Characteristics 38.3. Block Diagram 38.4. I/O Lines Description 38.5. Product Dependencies 38.5.1. I/O Lines 38.5.2. Power Management 38.5.3. Interrupt Sources 38.6. Functional Description 38.6.1. Timing Engine Configuration 38.6.1.1. Pixel Clock Period Configuration 38.6.1.2. Horizontal and Vertical Synchronization Configuration 38.6.1.3. Timing Engine Powerup Software Operation 38.6.1.4. Timing Engine Powerdown Software Operation 38.6.2. DMA Software Operations 38.6.2.1. DMA Channel Descriptor (DSCR) Alignment and Structure 38.6.2.2. Enabling a DMA Channel 38.6.2.3. Disabling a DMA Channel 38.6.2.4. DMA Dynamic Linking of a New Transfer Descriptor 38.6.2.5. DMA Interrupt Generation 38.6.2.6. DMA Address Alignment Requirements 38.6.3. Overlay Software Configuration 38.6.3.1. System Bus Access Attributes 38.6.3.2. Color Attributes 38.6.3.3. Window Position, Size, Scaling and Striding Attributes 38.6.3.4. Overlay Blender Attributes 38.6.3.5. Overlay Attributes Software Operation 38.6.4. RGB Frame Buffer Memory Bitmap 38.6.4.1. 1 bpp Through Color Lookup Table 38.6.4.2. 2 bpp Through Color Lookup Table 38.6.4.3. 4 bpp Through Color Lookup Table 38.6.4.4. 8 bpp Through Color Lookup Table 38.6.4.5. 12 bpp Memory Mapping, RGB 4:4:4 38.6.4.6. 16 bpp Memory Mapping with Alpha Channel, ARGB 4:4:4:4 38.6.4.7. 16 bpp Memory Mapping with Alpha Channel, RGBA 4:4:4:4 38.6.4.8. 16 bpp Memory Mapping with Alpha Channel, RGB 5:6:5 38.6.4.9. 16 bpp Memory Mapping with Transparency Bit, ARGB 1:5:5:5 38.6.4.10. 18 bpp Unpacked Memory Mapping with Transparency Bit, RGB 6:6:6 38.6.4.11. 18 bpp Packed Memory Mapping with Transparency Bit, RGB 6:6:6 38.6.4.12. 19 bpp Unpacked Memory Mapping with Transparency Bit, RGB 1:6:6:6 38.6.4.13. 19 bpp Packed Memory Mapping with Transparency Bit, ARGB 1:6:6:6 38.6.4.14. 24 bpp Unpacked Memory Mapping, RGB 8:8:8 38.6.4.15. 24 bpp Packed Memory Mapping, RGB 8:8:8 38.6.4.16. 25 bpp Memory Mapping, ARGB 1:8:8:8 38.6.4.17. 32 bpp Memory Mapping, ARGB 8:8:8:8 38.6.4.18. 32 bpp Memory Mapping, RGBA 8:8:8:8 38.6.5. YUV Frame Buffer Memory Mapping 38.6.5.1. AYCbCr 4:4:4 Packed Frame Buffer Memory Mapping 38.6.5.2. 4:2:2 Packed Mode Frame Buffer Memory Mapping 38.6.5.3. 4:2:2 Semiplanar Mode Frame Buffer Memory Mapping 38.6.5.4. 4:2:2 Planar Mode Frame Buffer Memory Mapping 38.6.5.5. 4:2:0 Planar Mode Frame Buffer Memory Mapping 38.6.5.6. 4:2:0 Semiplanar Frame Buffer Memory Mapping 38.6.6. Chrominance Upsampling Unit 38.6.6.1. Chrominance Upsampling Algorithm 38.6.7. Line and Pixel Striding 38.6.7.1. Line Striding 38.6.7.2. Pixel Striding 38.6.8. Color Space Conversion Unit 38.6.9. Two-Dimension Scaler 38.6.9.1. Video Scaler Description 38.6.9.2. Horizontal Scaler 38.6.9.3. Vertical Scaler 38.6.10. Color Combine Unit 38.6.10.1. Window Overlay 38.6.10.2. Base Layer with Window Overlay Optimization 38.6.10.3. Overlay Blending 38.6.10.4. Window Blending 38.6.10.5. Color Keying 38.6.10.5.1. Source Color Keying 38.6.10.5.2. Destination Color Keying 38.6.11. LCDC PWM Controller 38.6.12. LCD Overall Performance 38.6.12.1. Color Lookup Table (CLUT) 38.6.12.2. RGB Mode Fetch Performance 38.6.12.3. YUV Mode Fetch Performance 38.6.13. Input FIFO 38.6.14. Output FIFO 38.6.15. Output Timing Generation 38.6.15.1. Active Display Timing Mode 38.6.16. Output Format 38.6.16.1. Active Mode Output Pin Assignment 38.7. Register Summary 38.7.1. LCD Controller Configuration Register 0 38.7.2. LCD Controller Configuration Register 1 38.7.3. LCD Controller Configuration Register 2 38.7.4. LCD Controller Configuration Register 3 38.7.5. LCD Controller Configuration Register 4 38.7.6. LCD Controller Configuration Register 5 38.7.7. LCD Controller Configuration Register 6 38.7.8. LCD Controller Configuration Register 7 38.7.9. LCD Controller Enable Register 38.7.10. LCD Controller Disable Register 38.7.11. LCD Controller Status Register 38.7.12. LCD Controller Interrupt Enable Register 38.7.13. LCD Controller Interrupt Disable Register 38.7.14. LCD Controller Interrupt Mask Register 38.7.15. LCD Controller Interrupt Status Register 38.7.16. LCD Controller Attribute Register 38.7.17. LCD Controller QoS Configuration Register 38.7.18. LCD Controller QoS 1 Metrics Register 38.7.19. LCD Controller QoS 2 Metrics Register 38.7.20. LCD Controller QoS 3 Metrics Register 38.7.21. LCD Controller QoS Min FIFO Level Register 38.7.22. Base Layer Channel Enable Register 38.7.23. Base Layer Channel Disable Register 38.7.24. Base Layer Channel Status Register 38.7.25. Base Layer Interrupt Enable Register 38.7.26. Base Layer Interrupt Disable Register 38.7.27. Base Layer Interrupt Mask Register 38.7.28. Base Layer Interrupt Status Register 38.7.29. Base DMA Head Register 38.7.30. Base DMA Address Register 38.7.31. Base DMA Control Register 38.7.32. Base DMA Next Register 38.7.33. Base Layer Configuration Register 0 38.7.34. Base Layer Configuration Register 1 38.7.35. Base Layer Configuration Register 2 38.7.36. Base Layer Configuration Register 3 38.7.37. Base Layer Configuration Register 4 38.7.38. Base Layer Configuration Register 5 38.7.39. Base Layer Configuration Register 6 38.7.40. Overlay 1 Channel Enable Register 38.7.41. Overlay 1 Channel Disable Register 38.7.42. Overlay 1 Channel Status Register 38.7.43. Overlay 1 Interrupt Enable Register 38.7.44. Overlay 1 Interrupt Disable Register 38.7.45. Overlay 1 Interrupt Mask Register 38.7.46. Overlay 1 Interrupt Status Register 38.7.47. Overlay 1 Head Register 38.7.48. Overlay 1 Address Register 38.7.49. Overlay 1 Control Register 38.7.50. Overlay 1 Next Register 38.7.51. Overlay 1 Configuration Register 0 38.7.52. Overlay 1 Configuration Register 1 38.7.53. Overlay 1 Configuration Register 2 38.7.54. Overlay 1 Configuration Register 3 38.7.55. Overlay 1 Configuration Register 4 38.7.56. Overlay 1 Configuration Register 5 38.7.57. Overlay 1 Configuration Register 6 38.7.58. Overlay 1 Configuration Register 7 38.7.59. Overlay 1 Configuration Register 8 38.7.60. Overlay 1 Configuration Register 9 38.7.61. Overlay 2 Channel Enable Register 38.7.62. Overlay 2 Channel Disable Register 38.7.63. Overlay 2 Channel Status Register 38.7.64. Overlay 2 Interrupt Enable Register 38.7.65. Overlay 2 Interrupt Disable Register 38.7.66. Overlay 2 Interrupt Mask Register 38.7.67. Overlay 2 Interrupt Status Register 38.7.68. Overlay 2 Head Register 38.7.69. Overlay 2 Address Register 38.7.70. Overlay 2 Control Register 38.7.71. Overlay 2 Next Register 38.7.72. Overlay 2 Configuration Register 0 38.7.73. Overlay 2 Configuration Register 1 38.7.74. Overlay 2 Configuration Register 2 38.7.75. Overlay 2 Configuration Register 3 38.7.76. Overlay 2 Configuration Register 4 38.7.77. Overlay 2 Configuration Register 5 38.7.78. Overlay 2 Configuration Register 6 38.7.79. Overlay 2 Configuration Register 7 38.7.80. Overlay 2 Configuration Register 8 38.7.81. Overlay 2 Configuration Register 9 38.7.82. High-End Overlay Channel Enable Register 38.7.83. High-End Overlay Channel Disable Register 38.7.84. High-End Overlay Channel Status Register 38.7.85. High-End Overlay Interrupt Enable Register 38.7.86. High-End Overlay Interrupt Disable Register 38.7.87. High-End Overlay Interrupt Mask Register 38.7.88. High-End Overlay Interrupt Status Register 38.7.89. High-End Overlay DMA Head Register 38.7.90. High-End Overlay DMA Address Register 38.7.91. High-End Overlay DMA Control Register 38.7.92. High-End Overlay DMA Next Register 38.7.93. High-End Overlay U-UV DMA Head Register 38.7.94. High-End Overlay U-UV DMA Address Register 38.7.95. High-End Overlay U-UV DMA Control Register 38.7.96. High-End Overlay U-UV DMA Next Register 38.7.97. High-End Overlay V DMA Head Register 38.7.98. High-End Overlay V DMA Address Register 38.7.99. High-End Overlay V DMA Control Register 38.7.100. High-End Overlay V DMA Next Register 38.7.101. High-End Overlay Configuration Register 0 38.7.102. High-End Overlay Configuration Register 1 38.7.103. High-End Overlay Configuration Register 2 38.7.104. High-End Overlay Configuration Register 3 38.7.105. High-End Overlay Configuration Register 4 38.7.106. High-End Overlay Configuration Register 5 38.7.107. High-End Overlay Configuration Register 6 38.7.108. High-End Overlay Configuration Register 7 38.7.109. High-End Overlay Configuration Register 8 38.7.110. High-End Overlay Configuration Register 9 38.7.111. High-End Overlay Configuration Register 10 38.7.112. High-End Overlay Configuration Register 11 38.7.113. High-End Overlay Configuration Register 12 38.7.114. High-End Overlay Configuration Register 13 38.7.115. High-End Overlay Configuration Register 14 38.7.116. High-End Overlay Configuration Register 15 38.7.117. High-End Overlay Configuration Register 16 38.7.118. High-End Overlay Configuration Register 17 38.7.119. High-End Overlay Configuration Register 18 38.7.120. High-End Overlay Configuration Register 19 38.7.121. High-End Overlay Configuration Register 20 38.7.122. High-End Overlay Configuration Register 21 38.7.123. High-End Overlay Configuration Register 22 38.7.124. High-End Overlay Configuration Register 23 38.7.125. High-End Overlay Configuration Register 24 38.7.126. High-End Overlay Configuration Register 25 38.7.127. High-End Overlay Configuration Register 26 38.7.128. High-End Overlay Configuration Register 27 38.7.129. High-End Overlay Configuration Register 28 38.7.130. High-End Overlay Configuration Register 29 38.7.131. High-End Overlay Configuration Register 30 38.7.132. High-End Overlay Configuration Register 31 38.7.133. High-End Overlay Configuration Register 32 38.7.134. High-End Overlay Configuration Register 33 38.7.135. High-End Overlay Configuration Register 34 38.7.136. High-End Overlay Configuration Register 35 38.7.137. High-End Overlay Configuration Register 36 38.7.138. High-End Overlay Configuration Register 37 38.7.139. High-End Overlay Configuration Register 38 38.7.140. High-End Overlay Configuration Register 39 38.7.141. High-End Overlay Configuration Register 40 38.7.142. High-End Overlay Configuration Register 41 38.7.143. Base CLUT Register x 38.7.144. Overlay 1 CLUT Register x 38.7.145. Overlay 2 CLUT Register x 38.7.146. High-End Overlay CLUT Register x 39. 2D Graphics Engine (GFX2D) 39.1. Description 39.2. Embedded Characteristics 39.3. Block Diagram 39.4. Functional Description 39.4.1. Ring Buffer Management 39.4.1.1. Ring Buffer Model Diagram 39.4.1.2. Ring Buffer Allocation 39.4.1.3. Ring Buffer Push-Pull Model 39.4.1.4. Ring Buffer Disable 39.4.2. GFX2D Surface Memory Format 39.4.2.1. Source Surface Memory Format 39.4.2.1.1. 4-bit Alpha Channel with 4-bit Indexed Color 39.4.2.1.2. 8-bit Alpha Channel 39.4.2.1.3. 8-bit Indexed Color 39.4.2.1.4. 8-bit Alpha Channel with 8-bit Indexed Color 39.4.2.1.5. 12-bpp Memory Mapping, RGB 4:4:4 39.4.2.1.6. 16-bpp Memory Mapping with 4-bit Alpha Channel, ARGB 4:4:4:4 39.4.2.1.7. 16-bpp Memory Mapping with Transparency Bit, TRGB 5:5:5 39.4.2.1.8. 16-bpp Memory Mapping with Transparency Bit, RGBT 5:5:5:1 39.4.2.1.9. 16-bpp Memory Mapping with Alpha Channel, RGB 5:6:5 39.4.2.1.10. 32-bpp Memory Mapping, ARGB 8:8:8:8 39.4.2.1.11. 32-bpp Memory Mapping, RGBA 8:8:8:8 39.4.2.2. Destination Surface Memory Format 39.4.2.2.1. 4-bit Alpha Channel with 4-bit Luminance 39.4.2.2.2. 8-bit Alpha Channel 39.4.2.2.3. 8-bit Luminance Channel 39.4.2.2.4. 8-bit Alpha Channel with 8-bit Luminance 39.4.2.3. Color Look-Up Table (CLUT) 39.4.3. GFX2D Visible Registers 39.4.3.1. Register Naming 39.4.3.2. Register Descriptions 39.4.4. Traffic Balancing Using Outstanding Regulation 39.4.5. Data Flow Instructions 39.4.5.1. LDR Instruction 39.4.5.1.1. LDR_WD0 39.4.5.1.2. LDR_WD1 39.4.5.2. STR Instruction 39.4.5.2.1. STR_WD0 39.4.5.3. WFE Instruction 39.4.5.3.1. WFE_WD0 39.4.6. Graphics Instructions 39.4.6.1. FILL Instruction 39.4.6.1.1. FILL_WD0 39.4.6.1.2. FILL_WD1 39.4.6.1.3. FILL_WD2 39.4.6.1.4. FILL_WD3 39.4.6.2. COPY Instruction 39.4.6.2.1. COPY_WD0 39.4.6.2.2. COPY_WD1 39.4.6.2.3. COPY_WD2 39.4.6.2.4. COPY_WD3 39.4.6.3. BLEND Instruction 39.4.6.3.1. BLEND_WD0 39.4.6.3.2. BLEND_WD1 39.4.6.3.3. BLEND_WD2 39.4.6.3.4. BLEND_WD3 39.4.6.3.5. BLEND_WD3 39.4.6.3.6. BLEND_WD5 39.4.6.4. ROP Instruction 39.4.6.4.1. ROP_WD0 39.4.6.4.2. ROP_WD1 39.4.6.4.3. ROP_WD2 39.4.6.4.4. ROP_WD3 39.4.6.4.5. ROP_WD4 39.4.6.4.6. ROP_WD5 39.4.6.4.7. ROP_WD6 39.5. Register Summary 39.5.1. GFX2D Global Configuration Register 39.5.2. GFX2D Global Enable Register 39.5.3. GFX2D Global Disable Register 39.5.4. GFX2D Global Status Register 39.5.5. GFX2D Interrupt Enable Register 39.5.6. GFX2D Interrupt Disable Register 39.5.7. GFX2D Interrupt Mask Register 39.5.8. GFX2D Interrupt Status Register 39.5.9. GFX2D Performance Configuration 0 Register 39.5.10. GFX2D Metrics Counter 0 Register 39.5.11. GFX2D Performance Configuration 1 Register 39.5.12. GFX2D Metrics Counter 1 39.5.13. GFX2D Ring Buffer Base Register 39.5.14. GFX2D Ring Buffer Length Register 39.5.15. GFX2D Ring Buffer Head Register 39.5.16. GFX2D Ring Buffer Tail Register 39.5.17. GFX2D Surface x Physical Address Register 39.5.18. GFX2D Surface x Pitch Register 39.5.19. GFX2D Surface x Configuration Register 40. Ethernet MAC 10/100 (EMAC) 40.1. Description 40.2. Embedded Characteristics 40.3. Block Diagram 40.4. Functional Description 40.4.1. Clock 40.4.2. Memory Interface 40.4.2.1. FIFO 40.4.2.2. Receive Buffers 40.4.2.3. Transmit Buffer 40.4.3. Transmit Block 40.4.4. Pause Frame Support 40.4.5. Receive Block 40.4.6. Address Checking Block 40.4.7. Broadcast Address 40.4.8. Hash Addressing 40.4.9. External Address Matching 40.4.10. Copy All Frames (or Promiscuous Mode) 40.4.11. Type ID Checking 40.4.12. VLAN Support 40.4.13. Wake-on-LAN Support 40.4.14. PHY Maintenance 40.4.15. Physical Interface 40.4.15.1. RMII Transmit and Receive Operation 40.5. Programming Interface 40.5.1. Initialization 40.5.1.1. Configuration 40.5.1.2. Receive Buffer List 40.5.1.3. Transmit Buffer List 40.5.1.4. Address Matching 40.5.1.5. Interrupts 40.5.1.6. Transmitting Frames 40.5.1.7. Receiving Frames 40.6. Register Summary 40.6.1. Network Control Register 40.6.2. Network Configuration Register 40.6.3. Network Status Register 40.6.4. Transmit Status Register 40.6.5. Receive Buffer Queue Pointer Register 40.6.6. Transmit Buffer Queue Pointer Register 40.6.7. Receive Status Register 40.6.8. Interrupt Status Register 40.6.9. Interrupt Enable Register 40.6.10. Interrupt Disable Register 40.6.11. Interrupt Mask Register 40.6.12. PHY Maintenance Register 40.6.13. Pause Time Register 40.6.14. EMAC Statistics Registers 40.6.15. EMAC_FTO 40.6.16. EMAC_SCF 40.6.17. EMAC_MCF 40.6.18. EMAC_FRO 40.6.19. EMAC_FCSE 40.6.20. EMAC_ALE 40.6.21. EMAC_DTF 40.6.22. EMAC_LCOL 40.6.23. EMAC_ECOL 40.6.24. EMAC_TUND 40.6.25. EMAC_CSE 40.6.26. EMAC_RRE 40.6.27. EMAC_ROV 40.6.28. EMAC_RSE 40.6.29. EMAC_ELE 40.6.30. EMAC_RJA 40.6.31. EMAC_USF 40.6.32. EMAC_STE 40.6.33. EMAC_RLE 40.6.34. EMAC_TPF 40.6.35. Hash Register Bottom 40.6.36. Hash Register Top 40.6.37. Specific Address 1 Bottom Register 40.6.38. Specific Address 1 Top Register 40.6.39. Specific Address 2 Bottom Register 40.6.40. Specific Address 2 Top Register 40.6.41. Specific Address 3 Bottom Register 40.6.42. Specific Address 3 Top Register 40.6.43. Specific Address 4 Bottom Register 40.6.44. Specific Address 4 Top Register 40.6.45. Type ID Checking Register 40.6.46. Transmit Pause Quantum Register 40.6.47. User Input/Output Register 40.6.48. Wake-on-LAN Register 41. USB High Speed Device Port (UDPHS) 41.1. Description 41.2. Embedded Characteristics 41.3. Block Diagram 41.4. Typical Connection 41.5. Product Dependencies 41.5.1. Power Management 41.5.2. Interrupt Sources 41.6. Functional Description 41.6.1. UTMI Transceivers Sharing 41.6.2. USB V2.0 High Speed Device Port Introduction 41.6.3. USB V2.0 High Speed Transfer Types 41.6.4. USB Transfer Event Definitions 41.6.5. USB V2.0 High Speed BUS Transactions 41.6.6. Endpoint Configuration 41.6.7. DPRAM Management 41.6.8. Transfer With DMA 41.6.9. Transfer Without DMA 41.6.10. Handling Transactions with USB V2.0 Device Peripheral 41.6.10.1. Setup Transaction 41.6.10.2. NYET 41.6.10.3. Data IN 41.6.10.4. Data OUT 41.6.10.5. STALL 41.6.11. Speed Identification 41.6.12. USB V2.0 High Speed Global Interrupt 41.6.13. Endpoint Interrupts 41.6.14. Power Modes 41.6.14.1. Controlling Device States 41.6.14.2. Not Powered State 41.6.14.3. Entering Attached State 41.6.14.4. From Powered State to Default State (Reset) 41.6.14.5. From Default State to Address State (Address Assigned) 41.6.14.6. From Address State to Configured State (Device Configured) 41.6.14.7. Entering Suspend State (Bus Activity) 41.6.14.8. Receiving a Host Resume 41.6.14.9. Sending an External Resume 41.6.15. Test Mode 41.7. Register Summary 41.7.1. UDPHS Control Register 41.7.2. UDPHS Frame Number Register 41.7.3. UDPHS Interrupt Enable Register 41.7.4. UDPHS Interrupt Status Register 41.7.5. UDPHS Clear Interrupt Register 41.7.6. UDPHS Endpoints Reset Register 41.7.7. UDPHS Test Register 41.7.8. UDPHS Endpoint Configuration Register 41.7.9. UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints) 41.7.10. UDPHS Endpoint Control Enable Register (Isochronous Endpoints) 41.7.11. UDPHS Endpoint Control Disable Register (Control, Bulk, Interrupt Endpoints) 41.7.12. UDPHS Endpoint Control Disable Register (Isochronous Endpoint) 41.7.13. UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints) 41.7.14. UDPHS Endpoint Control Register (Isochronous Endpoint) 41.7.15. UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints) 41.7.16. UDPHS Endpoint Set Status Register (Isochronous Endpoint) 41.7.17. UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints) 41.7.18. UDPHS Endpoint Clear Status Register (Isochronous Endpoint) 41.7.19. UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints) 41.7.20. UDPHS Endpoint Status Register (Isochronous Endpoint) 41.7.21. UDPHS DMA Channel Transfer Descriptor 41.7.22. UDPHS DMA Next Descriptor Address Register 41.7.23. UDPHS DMA Channel Address Register 41.7.24. UDPHS DMA Channel Control Register 41.7.25. UDPHS DMA Channel Status Register 42. USB Host High Speed Port (UHPHS) 42.1. Description 42.2. Embedded Characteristics 42.3. Block Diagram 42.4. Typical Connection 42.5. Product Dependencies 42.5.1. I/O Lines 42.5.2. Power Management 42.5.3. Interrupt Sources 42.6. Functional Description 42.6.1. UTMI Transceivers Sharing 42.6.2. EHCI 42.6.3. OHCI 42.7. Register Summary 42.7.1. UHPHS Host Controller Capability Register 42.7.2. UHPHS Host Controller Structural Parameters Register 42.7.3. UHPHS Host Controller Capability Parameters Register 42.7.4. UHPHS USB Command Register 42.7.5. UHPHS USB Status Register 42.7.6. UHPHS USB Interrupt Enable Register 42.7.7. UHPHS USB Frame Index Register 42.7.8. UHPHS Periodic Frame List Base Address Register 42.7.9. UHPHS Asynchronous List Address Register 42.7.10. UHPHS Configure Flag Register 42.7.11. UHPHS Port Status and Control Register 42.7.12. EHCI: REG06 - AHB Error Status 42.7.13. EHCI: REG07 - AHB Master Error Address 43. Audio Class D Amplifier (CLASSD) 43.1. Description 43.2. Embedded Characteristics 43.3. Block Diagram 43.4. Pin Name List 43.5. Product Dependencies 43.5.1. I/O Lines 43.5.2. Power Management 43.5.3. Interrupt 43.6. Functional Description 43.6.1. Interpolator 43.6.1.1. Clock Configuration 43.6.1.2. CLASSD Frequency Response 43.6.2. Equalizer 43.6.3. De-emphasis Filter Frequency Response 43.6.4. Attenuator and Recommended Input Levels 43.6.5. Pulse Width Modulator (PWM) 43.6.6. Application Schematics For Use Case Examples 43.6.7. Register Write Protection 43.7. Register Summary 43.7.1. CLASSD Control Register 43.7.2. CLASSD Mode Register 43.7.3. CLASSD Interpolator Mode Register 43.7.4. CLASSD Interpolator Status Register 43.7.5. CLASSD Transmit Holding Register 43.7.6. CLASSD Interrupt Enable Register 43.7.7. CLASSD Interrupt Disable Register 43.7.8. CLASSD Interrupt Mask Register 43.7.9. CLASSD Interrupt Status Register 43.7.10. CLASSD Write Protection Mode Register 44. Inter-IC Sound Multi-Channel Controller (I2SMCC) 44.1. Description 44.2. Embedded Characteristics 44.3. Block Diagram 44.4. I/O Lines Description 44.5. Product Dependencies 44.5.1. I/O Lines 44.5.2. Power Management 44.5.3. Clocks 44.5.4. DMA Controller 44.5.5. Interrupt Sources 44.6. Functional Description 44.6.1. Initialization 44.6.2. Basic Operation 44.6.3. Master, Controller and Slave Modes 44.6.4. I2S Reception and Transmission Sequence 44.6.5. Left-Justified Reception and Transmission Sequence 44.6.6. TDM Reception and Transmission Sequence 44.6.7. Serial Clock and Word Select Generation 44.6.8. Mono 44.6.9. Holding Registers 44.6.9.1. Common Registers 44.6.10. DMA Controller Operation 44.6.11. Loop-back Mode 44.6.12. Interrupts 44.6.13. Register Write Protection 44.7. Register Summary 44.7.1. Inter-IC Sound Multi Channel Controller Control Register 44.7.2. Inter-IC Sound Multi Channel Controller Mode Register A 44.7.3. Inter-IC Sound Multi Channel Controller Mode Register B 44.7.4. Inter-IC Sound Multi Channel Controller Status Register 44.7.5. Inter-IC Sound Multi Channel Controller Interrupt Enable Register A 44.7.6. Inter-IC Sound Multi Channel Controller Interrupt Disable Register A 44.7.7. Inter-IC Sound Multi Channel Controller Interrupt Mask Register A 44.7.8. Inter-IC Sound Multi Channel Controller Interrupt Status Register A 44.7.9. Inter-IC Sound Multi Channel Controller Interrupt Enable Register B 44.7.10. Inter-IC Sound Multi Channel Controller Interrupt Disable Register B 44.7.11. Inter-IC Sound Multi Channel Controller Interrupt Mask Register B 44.7.12. Inter-IC Sound Multi Channel Controller Interrupt Status Register B 44.7.13. Inter-IC Sound Multi Channel Controller Receiver Holding Register 44.7.14. Inter-IC Sound Multi Channel Controller Transmitter Holding Register 44.7.15. Inter-IC Sound Write Protection Mode Register 44.7.16. Inter-IC Sound Write Protection Status Register 45. Synchronous Serial Controller (SSC) 45.1. Description 45.2. Embedded Characteristics 45.3. Block Diagram 45.4. Application Block Diagram 45.5. SSC Application Examples 45.6. Pin Name List 45.7. Product Dependencies 45.7.1. I/O Lines 45.7.2. Power Management 45.7.3. Interrupt 45.8. Functional Description 45.8.1. Clock Management 45.8.1.1. Clock Divider 45.8.1.2. Transmit Clock Management 45.8.1.3. Receive Clock Management 45.8.1.4. Serial Clock Ratio Considerations 45.8.2. Transmit Operations 45.8.3. Receive Operations 45.8.4. Start 45.8.5. Frame Synchronization 45.8.5.1. Frame Sync Data 45.8.5.2. Frame Sync Edge Detection 45.8.6. Receive Compare Modes 45.8.6.1. Compare Functions 45.8.7. Data Format 45.8.8. Loop Mode 45.8.9. Interrupt 45.8.10. Register Write Protection 45.9. Register Summary 45.9.1. SSC Control Register 45.9.2. SSC Clock Mode Register 45.9.3. SSC Receive Clock Mode Register 45.9.4. SSC Receive Frame Mode Register 45.9.5. SSC Transmit Clock Mode Register 45.9.6. SSC Transmit Frame Mode Register 45.9.7. SSC Receive Holding Register 45.9.8. SSC Transmit Holding Register 45.9.9. SSC Receive Synchronization Holding Register 45.9.10. SSC Transmit Synchronization Holding Register 45.9.11. SSC Receive Compare 0 Register 45.9.12. SSC Receive Compare 1 Register 45.9.13. SSC Status Register 45.9.14. SSC Interrupt Enable Register 45.9.15. SSC Interrupt Disable Register 45.9.16. SSC Interrupt Mask Register 45.9.17. SSC Write Protection Mode Register 45.9.18. SSC Write Protection Status Register 46. Flexible Serial Communication Controller (FLEXCOM) 46.1. Description 46.2. Embedded Characteristics 46.2.1. USART/UART Characteristics 46.2.2. SPI Characteristics 46.2.3. TWI/SMBus Characteristics 46.3. Block Diagram 46.4. I/O Lines Description 46.5. Product Dependencies 46.5.1. I/O Lines 46.5.2. Power Management 46.5.3. Interrupt Sources 46.6. Register Accesses 46.7. USART Functional Description 46.7.1. Baud Rate Generator 46.7.1.1. Baud Rate in Asynchronous Mode 46.7.1.1.1. Baud Rate Calculation Example 46.7.1.2. Fractional Baud Rate in Asynchronous Mode 46.7.1.3. Baud Rate in Synchronous Mode 46.7.1.4. Baud Rate in ISO 7816 Mode 46.7.2. Receiver and Transmitter Control 46.7.3. Synchronous and Asynchronous Modes 46.7.3.1. Transmitter Operations 46.7.3.2. Manchester Encoder 46.7.3.2.1. Drift Compensation 46.7.3.3. Asynchronous Receiver 46.7.3.4. Manchester Decoder 46.7.3.5. Radio Interface: Manchester Encoded USART Application 46.7.3.6. Synchronous Receiver 46.7.3.7. Receiver Operations 46.7.3.8. Parity 46.7.3.9. Multidrop Mode 46.7.3.10. Transmitter Timeguard 46.7.3.11. Receiver Timeout 46.7.3.12. Framing Error 46.7.3.13. Transmit Break 46.7.3.14. Receive Break 46.7.3.15. Hardware Handshaking 46.7.4. ISO7816 Mode 46.7.4.1. ISO7816 Mode Overview 46.7.4.2. Protocol T = 0 46.7.4.2.1. Receive Error Counter 46.7.4.2.2. Receive NACK Inhibit 46.7.4.2.3. Transmit Character Repetition 46.7.4.2.4. Disable Successive Receive NACK 46.7.4.3. Protocol T = 1 46.7.5. IrDA Mode 46.7.5.1. IrDA Modulation 46.7.5.2. IrDA Baud Rate 46.7.5.3. IrDA Demodulator 46.7.6. RS485 Mode 46.7.7. USART Comparison Function on Received Character 46.7.8. LIN Mode 46.7.8.1. Modes of Operation 46.7.8.2. Baud Rate Configuration 46.7.8.3. Receiver and Transmitter Control 46.7.8.4. Character Transmission 46.7.8.5. Character Reception 46.7.8.6. Header Transmission (Master Node Configuration) 46.7.8.7. Header Reception (Slave Node Configuration) 46.7.8.8. Slave Node Synchronization 46.7.8.9. Identifier Parity 46.7.8.10. Node Action 46.7.8.11. Response Data Length 46.7.8.12. Checksum 46.7.8.13. Frame Slot Mode 46.7.8.14. LIN Errors 46.7.8.14.1. Bit Error 46.7.8.14.2. Inconsistent Synch Field Error 46.7.8.14.3. Identifier Parity Error 46.7.8.14.4. Checksum Error 46.7.8.14.5. Slave Not Responding Error 46.7.8.14.6. Synch Tolerance Error 46.7.8.14.7. Header Timeout Error 46.7.8.15. LIN Frame Handling 46.7.8.15.1. Master Node Configuration 46.7.8.15.2. Slave Node Configuration 46.7.8.16. LIN Frame Handling with the DMA 46.7.8.16.1. Master Node Configuration 46.7.8.16.2. Slave Node Configuration 46.7.8.17. Wakeup Request 46.7.8.18. Bus Idle Timeout 46.7.9. LON Mode 46.7.9.1. Mode of Operation 46.7.9.2. Receiver and Transmitter Control 46.7.9.3. Character Transmission 46.7.9.4. Character Reception 46.7.9.5. LON Frame 46.7.9.5.1. Encoding / Decoding 46.7.9.5.2. Preamble Transmission 46.7.9.5.3. Preamble Reception 46.7.9.5.4. Header Transmission 46.7.9.5.5. Header Reception 46.7.9.5.6. Data 46.7.9.5.7. CRC 46.7.9.5.8. End Of Frame 46.7.9.6. LON Operating Modes 46.7.9.6.1. Transmitting/Receiving Modules 46.7.9.6.2. comm_type 46.7.9.6.3. Collision Detection 46.7.9.6.4. Collision Detection Mode 46.7.9.6.5. Collision Detection after CRC 46.7.9.6.6. Random Number Generation 46.7.9.7. LON Node Backlog Estimation 46.7.9.7.1. Optional Collision Detection Feature And Backlog Estimation 46.7.9.8. LON Timings 46.7.9.8.1. Beta2 46.7.9.8.2. Beta1 Tx/Rx 46.7.9.8.3. Pcycle Timer 46.7.9.8.4. Wbase 46.7.9.8.5. Priority Slots 46.7.9.8.6. Indeterminate Time 46.7.9.8.7. End of Frame Condition 46.7.9.9. LON Errors 46.7.9.9.1. Underrun Error 46.7.9.9.2. Collision Detection 46.7.9.9.3. LON Frame Early Termination 46.7.9.9.4. Reception Error 46.7.9.9.5. Backlog Overflow 46.7.9.10. Drift Compensation 46.7.9.11. LON Frame Handling 46.7.9.11.1. Sending a Frame 46.7.9.11.2. Receiving a Frame 46.7.9.12. LON Frame Handling with the Peripheral DMA Controller 46.7.9.12.1. Configuration 46.7.9.12.2. DMA and Collision Detection 46.7.10. Test Modes 46.7.10.1. Normal Mode 46.7.10.2. Automatic Echo Mode 46.7.10.3. Local Loopback Mode 46.7.10.4. Remote Loopback Mode 46.7.11. USART FIFOs 46.7.11.1. Overview 46.7.11.2. Sending Data with FIFO Enabled 46.7.11.3. Receiving Data with FIFO Enabled 46.7.11.4. Clearing/Flushing FIFOs 46.7.11.5. TXEMPTY, TXRDY and RXRDY Behavior 46.7.11.6. USART Single Data Mode 46.7.11.6.1. DMA 46.7.11.7. USART Multiple Data Mode 46.7.11.7.1. TXRDY and RXRDY Configuration 46.7.11.7.2. DMA 46.7.11.8. Transmit FIFO Lock 46.7.11.9. FIFO Pointer Error 46.7.11.10. FIFO Thresholds 46.7.11.11. FIFO Flags 46.7.12. 16-bit Data Protocol Support 46.7.13. USART Register Write Protection 46.8. SPI Functional Description 46.8.1. Modes of Operation 46.8.2. Data Transfer 46.8.3. Master Mode Operations 46.8.3.1. Master Mode Block Diagram 46.8.3.2. Master Mode Flowchart 46.8.3.3. Clock Generation 46.8.3.4. Transfer Delays 46.8.3.5. Peripheral Selection 46.8.3.6. SPI Direct Access Memory Controller (DMAC) 46.8.3.7. Peripheral Chip Select Decoding 46.8.3.8. Peripheral Deselection without DMA 46.8.3.9. Peripheral Deselection with DMA 46.8.3.10. Mode Fault Detection 46.8.4. SPI Slave Mode 46.8.5. SPI Comparison Function on Received Character 46.8.6. SPI FIFOs 46.8.6.1. Overview 46.8.6.2. Sending Data with FIFO Enabled 46.8.6.3. Receiving Data with FIFO Enabled 46.8.6.4. Clearing/Flushing FIFOs 46.8.6.5. TXEMPTY, TDRE and RDRF Behavior 46.8.6.6. SPI Single Data Mode 46.8.6.6.1. DMA 46.8.6.7. SPI Multiple Data Mode 46.8.6.7.1. TDRE and RDRF Configuration 46.8.6.7.2. DMA 46.8.6.8. FIFO Pointer Error 46.8.6.9. FIFO Thresholds 46.8.6.10. FIFO Flags 46.8.7. SPI Register Write Protection 46.9. TWI Functional Description 46.9.1. Transfer Format 46.9.2. Modes of Operation 46.9.3. Master Mode 46.9.3.1. Definition 46.9.3.2. Programming Master Mode 46.9.3.3. Transfer Speed/Bit Rate 46.9.3.4. Master Transmitter Mode 46.9.3.5. Master Receiver Mode 46.9.3.6. Internal Address 46.9.3.6.1. 7-bit Slave Addressing 46.9.3.6.2. 10-bit Slave Addressing 46.9.3.7. Repeated Start 46.9.3.8. Bus Clear Command 46.9.3.9. SMBus Mode 46.9.3.9.1. Packet Error Checking 46.9.3.9.2. Timeouts 46.9.3.10. SMBus Quick Command (Master Mode Only) 46.9.3.11. Alternative Command 46.9.3.12. Handling Errors in Alternative Command 46.9.3.13. Read/Write Flowcharts 46.9.4. Multi-Master Mode 46.9.4.1. Definition 46.9.4.2. Different Multi-Master Modes 46.9.4.2.1. TWI as Master Only 46.9.4.2.2. TWI as Master or Slave 46.9.5. Slave Mode 46.9.5.1. Definition 46.9.5.2. Programming Slave Mode 46.9.5.3. Receiving Data 46.9.5.3.1. Read Sequence 46.9.5.3.2. Write Sequence 46.9.5.3.3. Clock Stretching Sequence 46.9.5.3.4. General Call 46.9.5.4. Data Transfer 46.9.5.4.1. Read Operation 46.9.5.4.2. Write Operation 46.9.5.4.3. General Call 46.9.5.4.4. Clock Stretching 46.9.5.4.4.1. — Clock Stretching in Read Mode 46.9.5.4.4.2. — Clock Stretching in Write Mode 46.9.5.4.5. Reversal after a Repeated Start 46.9.5.4.5.1. — Reversal of Read to Write 46.9.5.4.5.2. — Reversal of Write to Read 46.9.5.4.6. SMBus Mode 46.9.5.4.6.1. — Packet Error Checking 46.9.5.4.6.2. — Timeouts 46.9.5.5. High-Speed Slave Mode 46.9.5.5.1. Read/Write Operation 46.9.5.5.2. Usage 46.9.5.6. Alternative Command 46.9.5.7. Slave Read/Write Flowcharts 46.9.6. TWI FIFOs 46.9.6.1. Overview 46.9.6.2. Sending Data with FIFO Enabled 46.9.6.3. Receiving Data with FIFO Enabled 46.9.6.4. Sending/Receiving with FIFO Enabled in Slave Mode 46.9.6.5. Clearing/Flushing FIFOs 46.9.6.6. TXRDY and RXRDY Behavior 46.9.6.7. TWI Single Data Mode 46.9.6.8. TWI Multiple Data Mode 46.9.6.8.1. TXRDY and RXRDY Configuration 46.9.6.8.2. DMA 46.9.6.9. Transmit FIFO Lock 46.9.6.10. FIFO Pointer Error 46.9.6.11. FIFO Thresholds 46.9.6.12. FIFO Flags 46.9.7. TWI Comparison Function on Received Character 46.9.8. Sniffer Mode 46.9.9. TWI Register Write Protection 46.10. Register Summary 46.10.1. FLEXCOM Mode Register 46.10.2. FLEXCOM Receive Holding Register 46.10.3. FLEXCOM Transmit Holding Register 46.10.4. USART Control Register 46.10.5. USART Mode Register 46.10.6. USART Interrupt Enable Register 46.10.7. USART Interrupt Enable Register (LIN_MODE) 46.10.8. USART Interrupt Enable Register (LON_MODE) 46.10.9. USART Interrupt Disable Register 46.10.10. USART Interrupt Disable Register (LIN_MODE) 46.10.11. USART Interrupt Disable Register (LON_MODE) 46.10.12. USART Interrupt Mask Register 46.10.13. USART Interrupt Mask Register (LIN_MODE) 46.10.14. USART Interrupt Mask Register (LON_MODE) 46.10.15. USART Channel Status Register 46.10.16. USART Channel Status Register (LIN_MODE) 46.10.17. USART Channel Status Register (LON_MODE) 46.10.18. USART Receive Holding Register 46.10.19. USART Receive Holding Register (FIFO Multi Data) 46.10.20. USART Transmit Holding Register 46.10.21. USART Transmit Holding Register (FIFO Multi Data) 46.10.22. USART Baud Rate Generator Register 46.10.23. USART Receiver Timeout Register 46.10.24. USART Transmitter Timeguard Register 46.10.25. USART Transmitter Timeguard Register (LON_MODE) 46.10.26. USART FI DI RATIO Register 46.10.27. USART FI DI RATIO Register (LON_MODE) 46.10.28. USART Number of Errors Register 46.10.29. USART IrDA FILTER Register 46.10.30. USART Manchester Configuration Register 46.10.31. USART LIN Mode Register 46.10.32. USART LIN Identifier Register 46.10.33. USART LIN Baud Rate Register 46.10.34. USART LON Mode Register 46.10.35. USART LON Preamble Register 46.10.36. USART LON Data Length Register 46.10.37. USART LON L2HDR Register 46.10.38. USART LON Backlog Register 46.10.39. USART LON Beta1 Tx Register 46.10.40. USART LON Beta1 Rx Register 46.10.41. USART LON Priority Register 46.10.42. USART LON IDT Tx Register 46.10.43. USART LON IDT Rx Register 46.10.44. USART IC DIFF Register 46.10.45. USART Comparison Register 46.10.46. USART FIFO Mode Register 46.10.47. USART FIFO Level Register 46.10.48. USART FIFO Interrupt Enable Register 46.10.49. USART FIFO Interrupt Disable Register 46.10.50. USART FIFO Interrupt Mask Register 46.10.51. USART FIFO Event Status Register 46.10.52. USART Write Protection Mode Register 46.10.53. USART Write Protection Status Register 46.10.54. SPI Control Register 46.10.55. SPI Mode Register 46.10.56. SPI Receive Data Register 46.10.57. SPI Receive Data Register (FIFO Multiple Data, 8-bit) 46.10.58. SPI Receive Data Register (FIFO Multiple Data, 16-bit) 46.10.59. SPI Transmit Data Register 46.10.60. SPI Transmit Data Register (FIFO Multiple Data, 8- to 16-bit) 46.10.61. SPI Status Register 46.10.62. SPI Interrupt Enable Register 46.10.63. SPI Interrupt Disable Register 46.10.64. SPI Interrupt Mask Register 46.10.65. SPI Chip Select Register 46.10.66. SPI FIFO Mode Register 46.10.67. SPI FIFO Level Register 46.10.68. SPI Comparison Register 46.10.69. SPI Write Protection Mode Register 46.10.70. SPI Write Protection Status Register 46.10.71. TWI Control Register 46.10.72. TWI Control Register (FIFO_ENABLED) 46.10.73. TWI Master Mode Register 46.10.74. TWI Slave Mode Register 46.10.75. TWI Internal Address Register 46.10.76. TWI Clock Waveform Generator Register 46.10.77. TWI Status Register 46.10.78. TWI Status Register (FIFO ENABLED) 46.10.79. TWI Interrupt Enable Register 46.10.80. TWI Interrupt Disable Register 46.10.81. TWI Interrupt Mask Register 46.10.82. TWI Receive Holding Register 46.10.83. TWI Receive Holding Register (FIFO Enabled) 46.10.84. TWI Transmit Holding Register 46.10.85. TWI Transmit Holding Register (FIFO Enabled) 46.10.86. TWI SMBus Timing Register 46.10.87. TWI Alternative Command Register 46.10.88. TWI Filter Register 46.10.89. TWI FIFO Mode Register 46.10.90. TWI FIFO Level Register 46.10.91. TWI FIFO Status Register 46.10.92. TWI FIFO Interrupt Enable Register 46.10.93. TWI FIFO Interrupt Disable Register 46.10.94. TWI FIFO Interrupt Mask Register 46.10.95. TWI Write Protection Mode Register 46.10.96. TWI Write Protection Status Register 47. Quad Serial Peripheral Interface (QSPI) 47.1. Description 47.2. Embedded Characteristics 47.3. Block Diagram 47.4. Signal Description 47.5. Product Dependencies 47.5.1. I/O Lines 47.5.2. Power Management 47.5.3. Interrupt Sources 47.5.4. Direct Memory Access Controller (DMA) 47.6. Functional Description 47.6.1. Serial Clock Baud Rate 47.6.2. Serial Clock Phase and Polarity 47.6.3. Transfer Delays 47.6.4. QSPI SPI Mode 47.6.4.1. SPI Mode Operations 47.6.4.2. SPI Mode Block Diagram 47.6.4.3. SPI Mode Flow Diagram 47.6.4.4. Peripheral Deselection without DMA 47.6.4.5. Peripheral Deselection with DMA 47.6.5. QSPI Serial Memory Mode 47.6.5.1. Instruction Frame 47.6.5.2. Instruction Frame Transmission 47.6.5.3. Read Memory Transfer 47.6.5.4. Continuous Read Mode 47.6.5.5. Instruction Frame Transmission Examples 47.6.6. Scrambling/Unscrambling Function 47.6.6.1. Clearing Scrambling Keys on a Tamper Event 47.6.7. Register Write Protection 47.7. Register Summary 47.7.1. QSPI Control Register 47.7.2. QSPI Mode Register 47.7.3. QSPI Receive Data Register 47.7.4. QSPI Transmit Data Register 47.7.5. QSPI Status Register 47.7.6. QSPI Interrupt Enable Register 47.7.7. QSPI Interrupt Disable Register 47.7.8. QSPI Interrupt Mask Register 47.7.9. QSPI Serial Clock Register 47.7.10. QSPI Instruction Address Register 47.7.11. QSPI Write Instruction Code Register 47.7.12. QSPI Instruction Frame Register 47.7.13. QSPI Read Instruction Code Register 47.7.14. QSPI Scrambling Mode Register 47.7.15. QSPI Scrambling Key Register 47.7.16. QSPI Write Protection Mode Register 47.7.17. QSPI Write Protection Status Register 48. Secure Digital MultiMedia Card Controller (SDMMC) 48.1. Description 48.2. Embedded Characteristics 48.3. Reference Documents 48.4. Block Diagram 48.5. Application Block Diagram 48.6. Pin Name List 48.7. Product Dependencies 48.7.1. I/O Lines 48.7.2. Power Management 48.7.3. Interrupt Sources 48.8. SD/SDIO Operating Mode 48.9. e.MMC Operating Mode 48.9.1. Boot Operation Mode 48.9.1.1. Boot Procedure, Processor Mode 48.9.1.2. Boot Procedure, SDMA Mode 48.9.1.3. Boot Procedure, ADMA Mode 48.10. Register Summary 48.10.1. SDMMC SDMA System Address / Argument 2 Register 48.10.2. SDMMC Block Size Register 48.10.3. SDMMC Block Count Register 48.10.4. SDMMC Argument 1 Register 48.10.5. SDMMC Transfer Mode Register 48.10.6. SDMMC Command Register 48.10.7. SDMMC Response Register x 48.10.8. SDMMC Buffer Data Port Register 48.10.9. SDMMC Present State Register 48.10.10. SDMMC Host Control 1 Register (SD_SDIO) 48.10.11. SDMMC Host Control 1 Register (e.MMC) 48.10.12. SDMMC Power Control Register 48.10.13. SDMMC Block Gap Control Register (SD_SDIO) 48.10.14. SDMMC Block Gap Control Register (e.MMC) 48.10.15. SDMMC Wakeup Control Register (SD_SDIO) 48.10.16. SDMMC Clock Control Register 48.10.17. SDMMC Timeout Control Register 48.10.18. SDMMC Software Reset Register 48.10.19. SDMMC Normal Interrupt Status Register (SD_SDIO) 48.10.20. SDMMC Normal Interrupt Status Register (e.MMC) 48.10.21. SDMMC Error Interrupt Status Register (SD_SDIO) 48.10.22. SDMMC Error Interrupt Status Register (e.MMC) 48.10.23. SDMMC Normal Interrupt Status Enable Register (SD_SDIO) 48.10.24. SDMMC Normal Interrupt Status Enable Register (e.MMC) 48.10.25. SDMMC Error Interrupt Status Enable Register (SD_SDIO) 48.10.26. SDMMC Error Interrupt Status Enable Register (e.MMC) 48.10.27. SDMMC Normal Interrupt Signal Enable Register (SD_SDIO) 48.10.28. SDMMC Normal Interrupt Signal Enable Register (e.MMC) 48.10.29. SDMMC Error Interrupt Signal Enable Register (SD_SDIO) 48.10.30. SDMMC Error Interrupt Signal Enable Register (e.MMC) 48.10.31. SDMMC Auto CMD Error Status Register 48.10.32. SDMMC Host Control 2 Register (SD_SDIO) 48.10.33. SDMMC Host Control 2 Register (e.MMC) 48.10.34. SDMMC Capabilities 0 Register 48.10.35. SDMMC Capabilities 1 Register 48.10.36. SDMMC Maximum Current Capabilities Register 48.10.37. SDMMC Force Event Register for Auto CMD Error Status 48.10.38. SDMMC Force Event Register for Error Interrupt Status 48.10.39. SDMMC ADMA Error Status Register 48.10.40. SDMMC ADMA System Address Register 0 48.10.41. SDMMC Preset Value Register 48.10.42. SDMMC Slot Interrupt Status Register 48.10.43. SDMMC Host Controller Version Register 48.10.44. SDMMC Additional Present State Register 48.10.45. SDMMC e.MMC Control 1 Register 48.10.46. SDMMC e.MMC Control 2 Register 48.10.47. SDMMC AHB Control Register 48.10.48. SDMMC Clock Control 2 Register 48.10.49. SDMMC Capabilities Control Register 48.10.50. SDMMC Debug Register 49. Image Sensor Interface (ISI) 49.1. Description 49.2. Embedded Characteristics 49.3. Block Diagram 49.4. Product Dependencies 49.4.1. I/O Lines 49.4.2. Power Management 49.4.3. Interrupt Sources 49.5. Functional Description 49.5.1. Data Timing 49.5.1.1. VSYNC/HSYNC Data Timing 49.5.1.2. SAV/EAV Data Timing 49.5.2. Data Ordering 49.5.3. Clocks 49.5.4. Preview Path 49.5.4.1. Scaling, Decimation (Subsampling) 49.5.4.2. Color Space Conversion 49.5.4.3. Memory Interface 49.5.4.3.1. RGB Mode 49.5.4.3.2. 12-bit Grayscale Mode 49.5.4.3.3. 8-bit Grayscale Mode 49.5.4.4. FIFO and DMA Features 49.5.5. Codec Path 49.5.5.1. Color Space Conversion 49.5.5.2. Memory Interface 49.5.5.3. DMA Features 49.5.6. Register Write Protection 49.6. Register Summary 49.6.1. ISI Configuration 1 Register 49.6.2. ISI Configuration 2 Register 49.6.3. ISI Preview Size Register 49.6.4. ISI Preview Decimation Factor Register 49.6.5. ISI Color Space Conversion YCrCb to RGB Set 0 Register 49.6.6. ISI Color Space Conversion YCrCb to RGB Set 1 Register 49.6.7. ISI Color Space Conversion RGB to YCrCb Set 0 Register 49.6.8. ISI Color Space Conversion RGB to YCrCb Set 1 Register 49.6.9. ISI Color Space Conversion RGB to YCrCb Set 2 Register 49.6.10. ISI Control Register 49.6.11. ISI Status Register 49.6.12. ISI Interrupt Enable Register 49.6.13. ISI Interrupt Disable Register 49.6.14. ISI Interrupt Mask Register 49.6.15. DMA Channel Enable Register 49.6.16. DMA Channel Disable Register 49.6.17. DMA Channel Status Register 49.6.18. DMA Preview Base Address Register 49.6.19. DMA Preview Control Register 49.6.20. DMA Preview Descriptor Address Register 49.6.21. DMA Codec Base Address Register 49.6.22. DMA Codec Control Register 49.6.23. DMA Codec Descriptor Address Register 49.6.24. ISI Write Protection Mode Register 49.6.25. ISI Write Protection Status Register 50. Controller Area Network (CAN) 50.1. Description 50.2. Embedded Characteristics 50.3. Block Diagram 50.4. Application Block Diagram 50.5. I/O Lines Description 50.6. Product Dependencies 50.6.1. I/O Lines 50.6.2. Power Management 50.6.3. Interrupt Sources 50.7. CAN Controller Features 50.7.1. CAN Protocol Overview 50.7.2. Mailbox Organization 50.7.2.1. Message Acceptance Procedure 50.7.2.2. Receive Mailbox 50.7.2.3. Transmit Mailbox 50.7.3. Time Management Unit 50.7.4. CAN 2.0 Standard Features 50.7.4.1. CAN Bit Timing Configuration 50.7.4.1.1. CAN Bus Synchronization 50.7.4.1.2. Autobaud Mode 50.7.4.2. Error Detection 50.7.4.2.1. Fault Confinement 50.7.4.2.2. Error Interrupt Handler 50.7.4.3. Overload 50.7.5. Low-power Mode 50.7.5.1. Enabling Low-power Mode 50.7.5.2. Disabling Low-power Mode 50.8. Functional Description 50.8.1. CAN Controller Initialization 50.8.2. CAN Controller Interrupt Handling 50.8.3. CAN Controller Message Handling 50.8.3.1. Receive Handling 50.8.3.1.1. Simple Receive Mailbox 50.8.3.1.2. Receive with Overwrite Mailbox 50.8.3.1.3. Chaining Mailboxes 50.8.3.2. Transmission Handling 50.8.3.3. Remote Frame Handling 50.8.3.3.1. Producer Configuration 50.8.3.3.2. Consumer Configuration 50.8.4. CAN Controller Timing Modes 50.8.4.1. Timestamping Mode 50.8.4.2. Time-triggered Mode 50.8.4.2.1. Synchronization by a Reference Message 50.8.4.2.2. Transmitting within a Time Window 50.8.4.2.3. Freezing the Internal Timer Counter 50.8.5. Register Write Protection 50.9. Register Summary 50.9.1. CAN Mode Register 50.9.2. CAN Interrupt Enable Register 50.9.3. CAN Interrupt Disable Register 50.9.4. CAN Interrupt Mask Register 50.9.5. CAN Status Register 50.9.6. CAN Baudrate Register 50.9.7. CAN Timer Register 50.9.8. CAN Timestamp Register 50.9.9. CAN Error Counter Register 50.9.10. CAN Transfer Command Register 50.9.11. CAN Abort Command Register 50.9.12. CAN Write Protection Mode Register 50.9.13. CAN Write Protection Status Register 50.9.14. CAN Message Mode Register 50.9.15. CAN Message Acceptance Mask Register 50.9.16. CAN Message ID Register 50.9.17. CAN Message Family ID Register 50.9.18. CAN Message Status Register 50.9.19. CAN Message Data Low Register 50.9.20. CAN Message Data High Register 50.9.21. CAN Message Control Register 51. Timer Counter (TC) 51.1. Description 51.2. Embedded Characteristics 51.3. Block Diagram 51.4. Pin List 51.5. Product Dependencies 51.5.1. I/O Lines 51.5.2. Power Management 51.5.3. Interrupt Sources 51.5.4. Synchronization Inputs from PWM 51.6. Functional Description 51.6.1. Description 51.6.2. 32-bit Counter 51.6.3. Clock Selection 51.6.4. Clock Control 51.6.5. Operating Modes 51.6.6. Trigger 51.6.7. Capture Mode 51.6.8. Capture Registers A and B 51.6.9. Transfer with DMAC in Capture Mode 51.6.10. Trigger Conditions 51.6.11. Waveform Mode 51.6.12. Waveform Selection 51.6.12.1. WAVSEL = 00 51.6.12.2. WAVSEL = 10 51.6.12.3. WAVSEL = 01 51.6.12.4. WAVSEL = 11 51.6.13. External Event/Trigger Conditions 51.6.14. Synchronization with PWM 51.6.15. Output Controller 51.6.16. Quadrature Decoder 51.6.16.1. Description 51.6.16.2. Input Preprocessing 51.6.16.3. Direction Status and Change Detection 51.6.16.4. Position and Rotation Measurement 51.6.16.5. Speed Measurement 51.6.16.6. Detecting a Missing Index Pulse 51.6.16.7. Detecting a Badly Located Index 51.6.16.8. Detecting Contamination/Dust at Rotary Encoder Low Speed 51.6.16.9. Report of Filtered Pulses due to Contamination/Dust 51.6.17. 2-bit Gray Up/Down Counter for Stepper Motor 51.6.18. Register Write Protection 51.6.19. Security and Safety Analysis and Reports 51.7. Register Summary 51.7.1. TC Channel Control Register 51.7.2. TC Channel Mode Register: Capture Mode 51.7.3. TC Channel Mode Register: Waveform Mode 51.7.4. TC Stepper Motor Mode Register 51.7.5. TC Register AB 51.7.6. TC Counter Value Register 51.7.7. TC Register A 51.7.8. TC Register B 51.7.9. TC Register C 51.7.10. TC Interrupt Status Register 51.7.11. TC Interrupt Enable Register 51.7.12. TC Interrupt Disable Register 51.7.13. TC Interrupt Mask Register 51.7.14. TC Extended Mode Register 51.7.15. TC Channel Status Register 51.7.16. TC Safety Status Register 51.7.17. TC Block Control Register 51.7.18. TC Block Mode Register 51.7.19. TC QDEC Interrupt Enable Register 51.7.20. TC QDEC Interrupt Disable Register 51.7.21. TC QDEC Interrupt Mask Register 51.7.22. TC QDEC Interrupt Status Register 51.7.23. TC QDEC Status Register 51.7.24. TC Write Protection Mode Register 52. Pulse Width Modulation Controller (PWM) 52.1. Description 52.2. Embedded Characteristics 52.3. Block Diagram 52.4. I/O Lines Description 52.5. Product Dependencies 52.5.1. I/O Lines 52.5.2. Power Management 52.5.3. Interrupt Sources 52.6. Functional Description 52.6.1. PWM Clock Generator 52.6.2. PWM Channel 52.6.2.1. Block Diagram 52.6.2.2. Waveform Properties 52.6.3. PWM Controller Operations 52.6.3.1. Initialization 52.6.3.2. Source Clock Selection Criteria 52.6.3.3. Changing the Duty Cycle or the Period 52.7. Register Summary 52.7.1. PWM Mode Register 52.7.2. PWM Enable Register 52.7.3. PWM Disable Register 52.7.4. PWM Status Register 52.7.5. PWM Interrupt Enable Register 52.7.6. PWM Interrupt Disable Register 52.7.7. PWM Interrupt Mask Register 52.7.8. PWM Interrupt Status Register 52.7.9. PWM Channel Mode Register x 52.7.10. PWM Channel Duty Cycle Register x 52.7.11. PWM Channel Period Register 52.7.12. PWM Channel Counter Register x 52.7.13. PWM Channel Update Register x 53. Advanced Encryption Standard (AES) 53.1. Description 53.2. Embedded Characteristics 53.3. Product Dependencies 53.3.1. Power Management 53.3.2. Interrupt Sources 53.4. Functional Description 53.4.1. AES Register Endianness 53.4.2. Operating Modes 53.4.3. Last Output Data Mode (CBC-MAC) 53.4.3.1. Manual and Auto Modes 53.4.3.1.1. If AES_MR.LOD = 0 53.4.3.1.2. If AES_MR.LOD = 1 53.4.3.2. DMA Mode 53.4.3.2.1. If AES_MR.LOD = 0 53.4.3.2.2. If AES_MR.LOD = 1 53.4.4. Galois/Counter Mode (GCM) 53.4.4.1. Description 53.4.4.2. Key Writing and Automatic Hash Subkey Calculation 53.4.4.3. GCM Processing 53.4.4.3.1. Processing a Complete Message with Tag Generation 53.4.4.3.2. Processing a Complete Message without Tag Generation 53.4.4.3.3. Processing a Fragmented Message without Tag Generation 53.4.4.3.4. Manual GCM Tag Generation 53.4.4.3.5. Processing a Message with only AAD (GHASHH) 53.4.4.3.6. Processing a Single GF128 Multiplication 53.4.5. XEX-based Tweaked-codebook Mode (XTS) 53.4.5.1. XTS Processing Procedure 53.4.5.1.1. Encrypted Tweak Generation 53.4.5.1.2. Data Processing 53.4.6. Double Input Buffer 53.4.7. Temporary Secured Storage for Keys 53.4.8. Start Modes 53.4.8.1. Manual Mode 53.4.8.2. Auto Mode 53.4.8.3. DMA Mode 53.4.9. Automatic Padding Mode 53.4.9.1. IPSEC Padding 53.4.9.2. SSL Padding 53.4.9.3. Flags 53.4.10. Secure Protocol Layers Improved Performances 53.4.10.1. Cipher Mode 53.4.10.2. Decipher Mode 53.4.10.3. Encapsulating Security Payload (ESP) IPSec Examples 53.4.11. Security Features 53.4.11.1. Private Key Bus 53.4.11.2. Unspecified Register Access Detection 53.4.11.3. Clearing Key on Tamper Event 53.4.11.4. Register Write Protection 53.4.11.5. Security and Safety Analysis and Reports 53.5. Register Summary 53.5.1. AES Control Register 53.5.2. AES Mode Register 53.5.3. AES Interrupt Enable Register 53.5.4. AES Interrupt Disable Register 53.5.5. AES Interrupt Mask Register 53.5.6. AES Interrupt Status Register 53.5.7. AES Key Word Register x 53.5.8. AES Input Data Register x 53.5.9. AES Output Data Register x 53.5.10. AES Initialization Vector Register x 53.5.11. AES Additional Authenticated Data Length Register 53.5.12. AES Plaintext/Ciphertext Length Register 53.5.13. AES GCM Intermediate Hash Word Register x 53.5.14. AES GCM Authentication Tag Word Register x 53.5.15. AES GCM Encryption Counter Value Register 53.5.16. AES GCM H Word Register x 53.5.17. AES Extended Mode Register 53.5.18. AES Byte Counter Register 53.5.19. AES Tweak Word Register x 53.5.20. AES Alpha Word Register x 53.5.21. AES Write Protection Mode Register 53.5.22. AES Write Protection Status Register 54. Secure Hash Algorithm (SHA) 54.1. Description 54.2. Embedded Characteristics 54.3. Product Dependencies 54.3.1. Power Management 54.3.2. Interrupt Sources 54.4. Functional Description 54.4.1. SHA Algorithm 54.4.2. HMAC Algorithm 54.4.3. Processing Period 54.4.4. Double Input Buffer 54.4.5. Internal Registers for Initial Hash Value or Expected Hash Result 54.4.6. Automatic Padding 54.4.7. Automatic Check 54.4.8. Protocol Layers Improved Performances 54.4.9. Start Modes 54.4.9.1. Manual Mode 54.4.9.2. Auto Mode 54.4.9.3. DMA Mode 54.4.9.4. SHA Register Endianness 54.4.10. Security Features 54.4.10.1. Unspecified Register Access Detection 54.4.10.2. Register Write Protection 54.4.10.3. Security and Safety Analysis and Reports 54.5. Register Summary 54.5.1. SHA Control Register 54.5.2. SHA Mode Register 54.5.3. SHA Interrupt Enable Register 54.5.4. SHA Interrupt Disable Register 54.5.5. SHA Interrupt Mask Register 54.5.6. SHA Interrupt Status Register 54.5.7. SHA Message Size Register 54.5.8. SHA Bytes Count Register 54.5.9. SHA Input Data Register x 54.5.10. SHA Input/Output Data Register x 54.5.11. SHA Write Protection Mode Register 54.5.12. SHA Write Protection Status Register 55. Triple Data Encryption Standard (TDES) 55.1. Description 55.2. Embedded Characteristics 55.3. Product Dependencies 55.3.1. Power Management 55.3.2. Interrupt Sources 55.4. Functional Description 55.4.1. Operating Modes 55.4.2. Temporary Secured Storage for Keys 55.4.3. Start Modes 55.4.3.1. Manual Mode 55.4.3.2. Auto Mode 55.4.3.3. DMA Mode 55.4.4. Last Output Data Mode (CBC-MAC) 55.4.4.1. Manual and Auto Modes 55.4.4.1.1. TDES_MR.LOD = 0 55.4.4.1.2. TDES_MR.LOD = 1 55.4.4.2. DMA Mode 55.4.4.2.1. TDES_MR.LOD = 0 55.4.4.2.2. TDES_MR.LOD = 1 55.4.5. Security Features 55.4.5.1. Private Key Bus 55.4.5.2. Unspecified Register Access Detection 55.4.5.3. Clearing Key on Tamper Event 55.4.5.4. Register Write Protection 55.4.5.5. Security and Safety Analysis and Reports 55.5. Register Summary 55.5.1. TDES Control Register 55.5.2. TDES Mode Register 55.5.3. TDES Interrupt Enable Register 55.5.4. TDES Interrupt Disable Register 55.5.5. TDES Interrupt Mask Register 55.5.6. TDES Interrupt Status Register 55.5.7. TDES Key 1 Word Register y 55.5.8. TDES Key 2 Word Register y 55.5.9. TDES Key 3 Word Register y 55.5.10. TDES Input Data Register x 55.5.11. TDES Output Data Register x 55.5.12. TDES Initialization Vector Register x 55.5.13. TDES XTEA Rounds Register 55.5.14. TDES Write Protection Mode Register 55.5.15. TDES Write Protection Status Register 56. True Random Number Generator (TRNG) 56.1. Description 56.2. Embedded Characteristics 56.3. Block Diagram 56.4. Product Dependencies 56.4.1. Power Management 56.4.2. Interrupt Sources 56.5. Functional Description 56.5.1. Normal Operating Mode 56.5.2. Key Bus Operating Mode 56.5.3. Register Write Protection 56.5.4. Security and Safety Analysis and Reports 56.6. Register Summary 56.6.1. TRNG Control Register 56.6.2. TRNG Mode Register 56.6.3. TRNG Private Key Bus Control Register 56.6.4. TRNG Interrupt Enable Register 56.6.5. TRNG Interrupt Disable Register 56.6.6. TRNG Interrupt Mask Register 56.6.7. TRNG Interrupt Status Register 56.6.8. TRNG Output Data Register 56.6.9. TRNG Write Protection Mode Register 56.6.10. TRNG Write Protection Status Register 57. Analog-to-Digital Controller (ADC) 57.1. Description 57.2. Embedded Characteristics 57.3. Block Diagram 57.4. Signal Description 57.5. Product Dependencies 57.5.1. Power Management 57.5.2. Interrupt Sources 57.5.3. I/O Lines 57.5.4. Hardware Triggers 57.5.5. Fault Output 57.6. Functional Description 57.6.1. Analog-to-Digital Conversion 57.6.2. ADC Clock 57.6.3. ADC Reference Voltage 57.6.4. Conversion Resolution 57.6.5. Conversion Results 57.6.6. Conversion Results Format 57.6.7. Conversion Triggers 57.6.8. Sleep Mode and Conversion Sequencer 57.6.9. Comparison Window 57.6.10. Pseudo-differential, Differential and Single-ended Input Modes 57.6.10.1. Input-output Transfer Functions 57.6.11. ADC Timings 57.6.12. Last Channel Specific Measurement Trigger 57.6.13. Enhanced Resolution Mode and Digital Averaging Function 57.6.13.1. Enhanced Resolution Mode 57.6.13.2. Averaging Function versus Trigger Events 57.6.14. Automatic Error Correction 57.6.15. Touchscreen 57.6.15.1. Touchscreen Mode 57.6.15.2. 4-wire Resistive Touchscreen Principles 57.6.15.3. 4-wire Position Measurement Method 57.6.15.4. 4-wire Pressure Measurement Method 57.6.15.5. 5-wire Resistive Touchscreen Principles 57.6.15.6. 5-wire Position Measurement Method 57.6.15.7. Sequence and Noise Filtering 57.6.15.8. Measured Values, Registers and Flags 57.6.15.9. Pen Detect Method 57.6.16. Buffer Structure 57.6.16.1. Classic ADC Channels Only (Touchscreen Disabled) 57.6.16.2. Touchscreen Channels Only 57.6.16.3. Interleaved Channels 57.6.16.4. Pen Detection Status 57.6.17. Fault Event 57.6.18. Register Write Protection 57.7. Register Summary 57.7.1. ADC Control Register 57.7.2. ADC Mode Register 57.7.3. ADC Channel Sequence 1 Register 57.7.4. ADC Channel Sequence 2 Register 57.7.5. ADC Channel Enable Register 57.7.6. ADC Channel Disable Register 57.7.7. ADC Channel Status Register 57.7.8. ADC Last Converted Data Register 57.7.9. ADC Interrupt Enable Register 57.7.10. ADC Interrupt Disable Register 57.7.11. ADC Interrupt Mask Register 57.7.12. ADC Interrupt Status Register 57.7.13. ADC Last Channel Trigger Mode Register 57.7.14. ADC Last Channel Compare Window Register 57.7.15. ADC Overrun Status Register 57.7.16. ADC Extended Mode Register 57.7.17. ADC Compare Window Register 57.7.18. Channel Configuration Register 57.7.19. ADC Channel Data Register 57.7.20. ADC Analog Control Register 57.7.21. ADC Pseudo-Differential Register 57.7.22. ADC Touchscreen Mode Register 57.7.23. ADC Touchscreen X Position Register 57.7.24. ADC Touchscreen Y Position Register 57.7.25. ADC Touchscreen Pressure Register 57.7.26. ADC Trigger Register 57.7.27. ADC Correction Values Register 57.7.28. ADC Channel Error Correction Register 57.7.29. ADC Touchscreen Correction Values Register 57.7.30. ADC Write Protection Mode Register 57.7.31. ADC Write Protection Status Register 58. Electrical Characteristics 58.1. Electrical Parameters Usage 58.2. Absolute Maximum Ratings 58.3. Recommended Operating Conditions 58.4. Recommended Power Supply Sequencing 58.4.1. Power-up and Power-down 58.4.2. Backup Mode Entry and Wake-up 58.5. I/O Characteristics 58.5.1. I/O DC Characteristics 58.5.2. I/O AC Characteristics 58.5.2.1. Output Driver AC Characteristics 58.5.2.2. Input AC Characteristics 58.6. Digital Peripheral Characteristics 58.6.1. QSPI Characteristics 58.6.1.1. QSPI Supported Operation 58.6.1.2. Maximum QSPI Frequency 58.6.1.3. QSPI Timings 58.6.2. FLEXCOM Characteristics 58.6.2.1. Maximum FLEXCOM SPI Frequency 58.6.2.1.1. Master Write Mode 58.6.2.1.2. Master Read Mode 58.6.2.1.3. Slave Read Mode 58.6.2.1.4. Slave Write Mode 58.6.2.2. FLEXCOM SPI Timings 58.6.2.3. USART in Asynchronous Modes 58.6.2.4. TWI Timings 58.6.3. SDMMC Characteristics 58.6.4. MPDDRC and SDRAMC Characteristics 58.6.5. SMC Timings 58.6.5.1. Read Timings 58.6.5.2. Write Timings 58.6.6. SSC Timings 58.6.7. I2SMCC Timings 58.6.8. ISI Timings 58.6.9. EMAC Timings 58.6.9.1. Ethernet MAC MII Mode 58.6.9.2. Ethernet MAC RMII Mode 58.7. Analog Peripheral Characteristics 58.7.1. VDDOUT25 Voltage Regulator 58.7.2. VDDCORE Power-On-Reset 58.7.3. VDDIN33 Power-On-Reset 58.7.4. VDDBU Power-On-Reset 58.7.5. Slow RC Oscillator 58.7.6. Main RC Oscillator 58.7.7. 32.768 kHz Crystal Oscillator 58.7.8. Main Crystal Oscillator 58.7.9. Crystal Oscillator Design Considerations 58.7.10. PLL Characteristics 58.7.11. 12-bit ADC Characteristics 58.7.11.1. Track and Hold Time versus Source Impedance – Sampling Rate 58.7.12. HS USB Transceiver Characteristics 58.8. Power Consumption in Active Mode 58.8.1. Processor Power Consumption in Active Mode 58.8.2. System Power Consumption in Applicative Use Cases 58.9. Operation and Power Consumption in Low-Power Modes 58.9.1. Backup Mode 58.9.1.1. Operation 58.9.1.2. Power Consumption 58.9.2. ULP0, ULP1 and Idle Modes 58.9.2.1. ULP0 Operation 58.9.2.2. ULP1 Operation 58.9.2.3. Idle Mode Operation 58.9.2.4. Power Consumption in ULP0, ULP1 and Idle Modes 59. Mechanical Characteristics 59.1. 228-ball TFBGA Mechanical Characteristics 60. Marking 61. Ordering Information 62. Revision History 62.1. DS60001579D - 09/2020 62.2. DS60001579C - 07/2020 62.3. DS60001579B - 02/2020 62.4. DS60001579A - 10/2019 The Microchip Website Product Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service