PORTMUX Control for CCL

Name:
CCLROUTEA
Offset:
0x01
Reset:
0x00
Access:
-
Bit76543210
LUT3LUT2LUT1LUT0
AccessR/WR/WR/WR/W
Reset0000

Bit 3 – LUT3: CCL LUT 3 Output

CCL LUT 3 Output

Write this bit to ‘1’ to select alternative pin location for CCL LUT 3.

ValueNameDescription
0x0 DEFAULT CCL LUT3 on PF[3]
0x1 ALT1 CCL LUT3 on PF[6]

Bit 2 – LUT2: CCL LUT 2 Output

CCL LUT 2 Output

Write this bit to ‘1’ to select alternative pin location for CCL LUT 2.

ValueNameDescription
0x0 DEFAULT CCL LUT2 on PD[3]
0x1 ALT1 CCL LUT2 on PD[6]

Bit 1 – LUT1: CCL LUT 1 Output

CCL LUT 1 Output

Write this bit to ‘1’ to select alternative pin location for CCL LUT 1.

ValueNameDescription
0x0 DEFAULT CCL LUT1 on PC[3]
0x1 ALT1 CCL LUT1 on PC[6]

Bit 0 – LUT0: CCL LUT 0 Output

CCL LUT 0 Output

Write this bit to ‘1’ to select alternative pin location for CCL LUT 0.

ValueNameDescription
0x0 DEFAULT CCL LUT0 on PA[3]
0x1 ALT1 CCL LUT0 on PA[6]